Commit Graph

104 Commits

Author SHA1 Message Date
David Guillen Fandos 4f3c9a5e58 [all] Fix CPSR and CPU modes
gpsp doesn't differentiate between USER and SYSTEM mode, most likely
cause it is not that important for most games. This implements the modes
correctly and adds checks for privileged operations. Still some
bugs/hacks but it mostly fixes CPSR/SPSR reads/writes.

To implement PSR writes we are using a more refined masks and force mode
bit num. 4 to always be one. Reserved bits are forced to zero (this
needs to be validated on a real device).
2023-01-11 21:26:32 +01:00
David Guillen Fandos 90170e3389 [arm] Fix usermode "movs pc" causing invalid CPU state
A missing usermode check (present in MIPS and x86) causes user-mode
returns to attempt returning into another CPU mode, which causes a bunch
of issues, mainly going into an invalid CPU state and corrupting some
registers.

This fixes a couple of games only (Colin McRae Rally 2, TOCA World
Touring, Starsky & Hutch ...)
2023-01-05 21:29:20 +01:00
David Guillen Fandos b552d5eb7e Improve open bus reads on ARM/MIPS 2023-01-05 21:29:20 +01:00
David Guillen Fandos dbbefdf021 [arm] Implement movw/movt for ARMv7
This should speed it up a bit on platforms like Vita.
2022-01-05 17:12:35 +01:00
David Guillen Fandos cb9696cb98 Fix blh for arm/mips to use a thumb branch (not dual)
Also fix ARM32 LR offset, was being truncated to 8 bit when it is a 12
bit offset.
2022-01-04 19:11:36 +01:00
David Guillen Fandos 3a6ca8d941 Better cycle accounting, taking remainders partially into account 2021-12-21 19:59:33 +01:00
David Guillen Fandos 7b181cb6ff Fix PC calculation for open bus loads
It was pretty much broken in all platforms, just "ok" enough for it to
work on some games though.
2021-12-20 19:31:33 +01:00
David Guillen Fandos 12cd4e0c06 [aarch64] Add I/O write specific path for speed 2021-12-19 22:35:07 +01:00
David Guillen Fandos 5fbbcfe415 [aarch64] Add accelerated palette writes 2021-12-19 21:01:08 +01:00
David Guillen Fandos d0fd474777 [arm] Fix multiply (muls) and 64 bit mul where rlo==rhi
Seems rhi has precedence over rlo
2021-12-17 10:46:45 +01:00
David Guillen Fandos c6601d8932 [aarch64] Fix cache flushing out of bounds
Seems like some platforms don't like this very much :|
2021-12-13 18:54:21 +01:00
David Guillen Fandos 76ccba445f [aarch64] Fix mov bug that got in in the last minute :D 2021-12-13 18:49:42 +01:00
David Guillen Fandos bcd3d1ca29 [aarch64] Adding new aarch64 dynarec!
This is based on the MIPS dynarec (more or less) with some ARM
borrowings. Seems to be quite fast (under my testing fixed results:
faster than ARM on A1 but not a lot faster than the interpreter on
Android Snapdragon 845) but still some optimizations are missing at the
moment.

Seems to pass my testing suite and compatibility wise is very similar to
arm.
2021-12-12 13:18:13 +01:00
David Guillen Fandos 2419b77b28 Add reg tracing capability (for devs) 2021-12-11 11:27:59 +01:00
David Guillen Fandos a2aa78733d Further simplify stubs, remove unnecessary masking 2021-11-14 22:40:03 +01:00
David Guillen Fandos 6c4ffc4db2 [arm] Improve external stores and make them faster
While at it, speed up palette writes too.
2021-11-14 13:19:20 +01:00
David Guillen Fandos 92180d5d7e Minor unused stuff cleanup 2021-11-06 21:49:08 +01:00
David Guillen Fandos 3a7fedb8fb Simplify MMAP machinery for Win/Lin/Mac/Android
This gets rid of the bloated memmap_win32.c in favour of a much simpler
wrapper. This will be needed in the future since the wrapper does not
support MAP_FIXED maps (necessary for some platforms)
2021-11-05 18:23:05 +01:00
David Guillen Fandos 3f012afcda Make ROM hash table mechanism 64 bit compatible. 2021-10-30 22:54:51 +02:00
David Guillen Fandos c39f5391f0 [ARM] Start using mmap'ed JIT caches for most builds
Will revisit remaining platforms and try to clean them too.
This should fix Android once and for all.
2021-10-29 22:51:39 +02:00
David Guillen Fandos 5c1467cb63 [ARM] Remove cross calls between cache and text (far calls)
This is to allow cache to be mapped far from the regular .text section
2021-10-29 22:34:29 +02:00
David Guillen Fandos f65c3939b5 [ARM] Rewrite HLE emulation for div, make it faster and simpler.
Moves the handlers to the cache, removes C usage.
2021-10-24 18:00:06 +02:00
David Guillen Fandos b65df123f8 [ARM] Add support for ARMv5 2021-10-23 23:59:51 +02:00
David Guillen Fandos d558fb4fc4 [ARM] Rework memory handlers for speed amb simplicity
This removes one branch and emits the region selection code directly in
the JIT cache. Trading memory for speed (although it's not a big
improvement).

This is a step towards enabling MMAP caches in ARM (due to the 32MB
offset limitation in branches).
2021-10-23 23:33:15 +02:00
David Guillen Fandos 4bebb6135d Inline spsr operations 2021-10-23 12:02:46 +02:00
David Guillen Fandos d89977d25d Fix CPSR reads in ARM32
Interestingly enough, doesn't seem to affect more than a couple games.
2021-10-23 09:31:21 +02:00
David Guillen Fandos cdb61227bc Fix arm32 spsr writes: only write selected bits
Seems no game is affected, even though the current implementration is
broken. Most games seem to not use mask at all.
2021-10-23 09:06:24 +02:00
David Guillen Fandos 3cab8596b8 Fix SWI handling (disable IRQs)
This introduced a potential race condition between the start of a SWI
and the BIOS handling the exception by returning to system mode. During
this ~10 instruction window, having an IRQ that issues a SWI causes bad
behaviour that results in crashes or other weirdness.
Fixes a couple of games and potentially many weird and obscure bugs here
and there (hard to reproduce sometimes).
2021-09-17 22:22:01 +02:00
David Guillen Fandos 401adca6ae Cleanup unused stuff in mips and arm 2021-09-15 20:34:21 +02:00
David Guillen Fandos 33f1e25099 Emit BIOS SWI entrypoint to ROM arena
This fixes a race condition that happens whenever the ROM cache is flushed but
the RAM one is not, causing any SWI calls (implemented as direct branches) to
jump to random instructions.
The fix could be to flush both caches at the same time (~expensive on
low mem platforms), use indirect jumps (a bit expensive) or emit the SWI
handler below the watermark to ensure it is never flushed. This is cheap
and effective, requires minimal changes.
2021-09-10 00:30:55 +02:00
David Guillen Fandos f51ed9de13 Improve SWI codepaths and implement div&divarm natively 2021-09-03 01:01:37 +02:00
David Guillen Fandos 2295dc4a3a Fix bad ARM code emitter bug
This mis-emits CMN instead of TEQ and TST in the reg-shift operand mode.
This is never used by gpsp directly but translating real tst opcodes,
hence it only affects games using such instruction.

This fixes video players that previously crashed, many games that had
graphical glitches in ARM mode (but not on other CPUs) usually in menus
or other dialogues. Also fixes games that either crashed or went blank
or similar issues. The extent of fixing is hard to determine but could
affect many games in different levels.
2021-08-30 02:07:31 +02:00
David Guillen Fandos 55c6a69ccd Move flag regs to unserialized area
This is only used in x86 (mips and arm use native regs and never spill)
2021-08-28 17:50:25 +02:00
David Guillen Fandos f5232543f5 Improve tracing prints 2021-08-15 22:48:43 +02:00
David Guillen Fandos 057b80f8cc Fix a bug with BLH (half BL) on ARM
This fixes issues on games from Camelot (GS2 and Mario Golf)
2021-08-15 22:19:40 +02:00
David Guillen Fandos 14bc6e3554 Remove unnecessary check in update stub (arm) 2021-08-15 21:52:26 +02:00
David Guillen Fandos 5be5015338 Rearrange register layout and exclude useless regs from savestat
This changes the savestate format once again.
2021-08-15 21:07:20 +02:00
David Guillen Fandos ce14e2585b Fix and reenable Android arm 32 bit builds
Removed the last bits of text relocations by moving all relevant RAMs to
the stub reachable area. This should be as fast or even faster than
previous code.
2021-07-31 17:45:46 +02:00
David Guillen Fandos b3abefa7d9 Avoid using relocations in arm code 2021-07-31 00:20:18 +02:00
David Guillen Fandos ab7d9bb161 Move membuffers close to dynarec area to fix x86 relocs
This essentially makes it easier to get a relocation-free text area for
x86 so that Android loaders are happy.
2021-07-28 19:12:43 +02:00
David Guillen Fandos ae2a656e66 Remove nested functions in arm dynarec
Re-enable Android builds
2021-07-27 00:47:54 +02:00
David Guillen Fandos 72a4a91fda Speed up arm stores 2021-07-15 21:27:38 +02:00
David Guillen Fandos ac3e75a107 Reimplement arm load stubs and fix BIOS handler
This fixes unallowed BIOS accesses (outside from BIOS) which fixes some
games like Silent Scope but also Zelda (fixes rolling as reported by
neonloop!)
2021-07-15 00:40:52 +02:00
David Guillen Fandos 221b8ff115 Partially revert 71ebc49b
Just move the complex lookup to C for simplicity since there's not a lot
of gain to have. This makes it easier for devices with weird jit caches.
2021-07-14 01:59:46 +02:00
David Guillen Fandos 3144d9e277 Rework ram block ptrs to remove second indirection table.
This removes ram_block_ptrs and encodes the pointer directly in the
block tag. Saves ~256KB at no performance cost.
Drawback is that it limits the ram cache size to 512KB (we were using
768KB before). Should not be a problem since most games use less than
32KB of cache anyway.

Fixed ARM routines accordingly.
2021-07-08 21:29:48 +02:00
David Guillen Fandos ea2608812f Minor optimization 2021-05-19 20:11:35 +02:00
David Guillen Fandos aafde6de7b Add ROM mirroring and fix mult. cycle count
This should correct some minor issues in some games.
2021-05-17 01:16:56 +02:00
David Guillen Fandos 2877886ff1 Fix ARM dynarec unaligned 32 bit loads
This might make a handful games slightly slower (but on the upper side
they work now instead of crashing or restarting).
Also while at it, fix some minor stuff in arm stubs for speed.
2021-05-17 01:16:56 +02:00
David Guillen Fandos 37430f22c5 Small optimization (~2-4%) and whitespace cleanup!
Cleans up a ton of whitespace in cpu.c (like 100KB!) and improves
readability of some massive decode statements.

Added an optimization for PC-relative loads (pool load) in ROM (since
it's read only and cannot possibily change) that directly emits an
immediate load. This is way faster, specially in MIPS/x86, ARM can be
even faster if we rewrite the immediate load macros to also use a pool.
2021-05-07 20:41:54 +02:00
David Guillen Fandos 883f07f487 Fix small buf and add cheat error messages
Some minor formating too
2021-05-05 21:15:27 +02:00