[arm] Improve external stores and make them faster
While at it, speed up palette writes too.
This commit is contained in:
David Guillen Fandos
parent
fda42c959f
commit
6c4ffc4db2
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@ -1754,9 +1754,6 @@ static void trace_instruction(u32 pc, u32 mode)
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/* TODO: Make these use cached registers. Implement iwram_stack_optimize. */
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#define thumb_block_address_preadjust_up() \
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generate_add_imm(reg_s0, (bit_count[reg_list] * 4), 0) \
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#define thumb_block_address_preadjust_down() \
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generate_sub_imm(reg_s0, (bit_count[reg_list] * 4), 0) \
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@ -1772,11 +1769,6 @@ static void trace_instruction(u32 pc, u32 mode)
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generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
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thumb_generate_store_reg(reg_a0, base_reg) \
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#define thumb_block_address_postadjust_down(base_reg) \
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generate_mov(reg_a0, reg_s0); \
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generate_sub_imm(reg_a0, (bit_count[reg_list] * 4), 0); \
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thumb_generate_store_reg(reg_a0, base_reg) \
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#define thumb_block_address_postadjust_pop_pc(base_reg) \
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generate_add_reg_reg_imm(reg_a0, reg_s0, \
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((bit_count[reg_list] + 1) * 4), 0); \
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@ -77,6 +77,7 @@ _##symbol:
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#define PAL_RAM_OFF 0x900
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#define RDMAP_OFF 0xD00
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#define IOREG_OFF 0x8D00
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#define PAL_CONV_OFF 0x9100
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#if __ARM_ARCH >= 6
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@ -490,6 +491,15 @@ return_to_main:
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#define execute_store_builder(store_type, str_op, str_op16, load_op, tnum) ;\
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;\
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ext_store_u##store_type: ;\
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save_flags() ;\
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ldr r2, [lr] /* load PC */;\
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str r2, [reg_base, #REG_PC] /* write out PC */;\
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store_align_##store_type() ;\
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call_c_function(write_memory##store_type) ;\
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restore_flags() ;\
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add pc, lr, #4 /* return */;\
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;\
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ext_io_store_u##store_type: ;\
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save_flags() ;\
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ldr r2, [lr] /* load PC */;\
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str r2, [reg_base, #REG_PC] /* write out PC */;\
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@ -548,20 +558,20 @@ ext_store_ignore:
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add pc, lr, #4 @ return
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#define store_lookup_table(store_type) ;\
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.word ext_store_u##store_type /* -1: ignore, for > 0x0F */;\
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.word ext_store_ignore /* -1: ignore, for > 0x0F */;\
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.word ext_store_ignore /* 0x00: BIOS, ignore */;\
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.word ext_store_ignore /* 0x01: ignore */;\
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.word ext_store_ewram_u##store_type /* 0x02: ewram */;\
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.word ext_store_iwram_u##store_type /* 0x03: iwram */;\
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.word ext_store_u##store_type /* 0x04: I/O regs */;\
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.word ext_store_u##store_type /* 0x05: palette RAM */;\
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.word ext_io_store_u##store_type /* 0x04: I/O regs */;\
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.word ext_store_palette_u##store_type /* 0x05: palette RAM */;\
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.word ext_store_vram_u##store_type /* 0x06: vram */;\
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.word ext_store_oam_ram_u##store_type /* 0x07: oam ram */;\
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.word ext_store_u##store_type /* 0x08: gamepak: ignore */;\
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.word ext_store_u##store_type /* 0x09: gamepak: ignore */;\
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.word ext_store_u##store_type /* 0x0A: gamepak: ignore */;\
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.word ext_store_u##store_type /* 0x0B: gamepak: ignore */;\
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.word ext_store_u##store_type /* 0x0C: gamepak: ignore */;\
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.word ext_store_ignore /* 0x09: gamepak: ignore */;\
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.word ext_store_ignore /* 0x0A: gamepak: ignore */;\
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.word ext_store_ignore /* 0x0B: gamepak: ignore */;\
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.word ext_store_ignore /* 0x0C: gamepak: ignore */;\
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.word ext_store_u##store_type /* 0x0D: EEPROM */;\
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.word ext_store_u##store_type /* 0x0E: backup */;\
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.word ext_store_ignore /* 0x0F: ignore */;\
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@ -570,14 +580,62 @@ execute_store_builder(8, strb, strh, ldrb, 0)
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execute_store_builder(16, strh, strh, ldrh, 1)
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execute_store_builder(32, str, str, ldr, 2)
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@ Palette writes are special since they are converted on the fly for speed
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ext_store_palette_u8:
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bic r1, r1, #0xff00 // Duplicate the byte
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orr r1, r1, lsl #8
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ext_store_palette_u16:
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mask_addr_16(10) // Accesses are always 16 bit
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add r2, reg_base, #PAL_RAM_OFF // r2 = palette base
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strh r1, [r0, r2] // store data
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and r2, r1, #0x3E0 // Convert color point
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lsl r2, r2, #1
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orr r2, r1, lsl #11
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and r1, r1, #0x7C00
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orr r2, r1, lsr #10
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add r1, reg_base, #PAL_CONV_OFF // r1 = converted palette ram
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strh r2, [r0, r1] // Converted value write (r2)
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add pc, lr, #4 // return
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ext_store_palette_u32_safe:
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sub lr, lr, #4
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ext_store_palette_u32:
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mask_addr_32(10) // Accesses are always 16 bit
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add r2, reg_base, #PAL_RAM_OFF // r2 = palette base
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str r1, [r0, r2] // store data
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add r2, reg_base, #PAL_CONV_OFF // r2 = converted palette ram
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lsr r9, r1, #10
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and r9, r9, #0x1F
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orr r9, r1, lsl #11
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bic r1, r1, #0x1F
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bic r1, r1, #0xFC00
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orr r9, r1, lsl #1
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strh r9, [r0, r2] // Write first halfword
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add r0, r0, #2
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lsr r1, r1, #16
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and r9, r1, #0x3E0
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lsl r9, r9, #1
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orr r9, r1, lsl #11
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and r1, r1, #0x7C00
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orr r9, r1, lsr #10
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strh r9, [r0, r2] // Write second halfword
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add pc, lr, #4 // return
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@ This is a store that is executed in a strm case (so no SMC checks in-between)
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ext_store_u32_safe:
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str lr, [reg_base, #REG_SAVE3] @ Restore lr
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ext_io_store_u32_safe:
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save_flags()
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call_c_function(write_memory32) @ Perform 32bit store
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restore_flags()
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ldr pc, [reg_base, #REG_SAVE3] @ return
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bx lr @ Return
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ext_store_iwram_u32_safe:
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mask_addr_8(15) @ Mask to mirror memory (no need to align!)
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@ -834,7 +892,6 @@ defsymbl(memory_map_read)
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.space 0x8000
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defsymbl(io_registers)
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.space 0x400
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defsymbl(palette_ram_converted)
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.space 0x400
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