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Cleanup unused stuff in mips and arm

This commit is contained in:
David Guillen Fandos 2021-09-15 20:34:21 +02:00
parent 33f1e25099
commit 401adca6ae
2 changed files with 1 additions and 34 deletions
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28
arm/arm_emit.h
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@ -395,16 +395,6 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
cycle_count = 0; \
} \
#define generate_cycle_update_flag_set() \
if(cycle_count >> 8) \
{ \
ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count >> 8) & 0xFF, \
arm_imm_lsl_to_rot(8)); \
} \
generate_save_flags(); \
ARM_ADDS_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count & 0xFF), 0); \
cycle_count = 0 \
#define generate_branch_patch_conditional(dest, offset) \
*((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) | \
arm_relative_offset(dest, offset) \
@ -692,20 +682,12 @@ u32 execute_spsr_restore_body(u32 pc)
return pc;
}
#define generate_load_flags() \
/* ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR) */ \
#define generate_store_flags() \
/* ARM_MRS_CPSR(0, reg_flags) */ \
#define generate_save_flags() \
ARM_MRS_CPSR(0, reg_flags) \
#define generate_restore_flags() \
ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR) \
#define condition_opposite_eq ARMCOND_NE
#define condition_opposite_ne ARMCOND_EQ
#define condition_opposite_cs ARMCOND_CC
@ -939,9 +921,7 @@ u32 execute_spsr_restore_body(u32 pc)
} \
#define generate_op_muls_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
generate_load_flags(); \
ARM_MULS(0, _rd, _rn, _rm); \
generate_store_flags() \
#define generate_op_cmp_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
generate_op_reg_immshift_tflags(CMP, _rn, _rm, shift_type, shift) \
@ -1129,15 +1109,11 @@ u32 execute_spsr_restore_body(u32 pc)
ARM_MLA(0, _rd, _rm, _rs, _rn) \
#define arm_multiply_add_no_flags_yes() \
generate_load_flags(); \
ARM_MULS(0, reg_a0, reg_a0, reg_a1) \
generate_store_flags() \
#define arm_multiply_add_yes_flags_yes() \
u32 _rn = arm_prepare_load_reg(&translation_ptr, reg_a2, rn); \
generate_load_flags(); \
ARM_MLAS(0, _rd, _rm, _rs, _rn); \
generate_store_flags()
#define arm_multiply(add_op, flags) \
@ -1161,9 +1137,7 @@ u32 execute_spsr_restore_body(u32 pc)
ARM_##name(0, _rdlo, _rdhi, _rm, _rs) \
#define arm_multiply_long_flags_yes(name) \
generate_load_flags(); \
ARM_##name##S(0, _rdlo, _rdhi, _rm, _rs); \
generate_store_flags() \
#define arm_multiply_long_add_no(name) \
@ -1820,7 +1794,6 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
#define thumb_conditional_branch(condition) \
{ \
generate_cycle_update(); \
generate_load_flags(); \
generate_branch_filler(condition_opposite_##condition, backpatch_address); \
generate_branch_no_cycle_update( \
block_exits[block_exit_position].branch_source, \
@ -1832,7 +1805,6 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
#define arm_conditional_block_header() \
generate_cycle_update(); \
generate_load_flags(); \
/* This will choose the opposite condition */ \
condition ^= 0x01; \
generate_branch_filler(condition, backpatch_address) \

7
psp/mips_emit.h
View File

@ -497,14 +497,12 @@ u32 arm_to_mips_reg[] =
reg_r14,
reg_a0,
reg_a1,
reg_a2,
reg_temp
reg_a2
};
#define arm_reg_a0 15
#define arm_reg_a1 16
#define arm_reg_a2 17
#define arm_reg_temp 18
#define generate_load_reg(ireg, reg_index) \
mips_emit_addu(ireg, arm_to_mips_reg[reg_index], reg_zero) \
@ -668,9 +666,6 @@ u32 arm_to_mips_reg[] =
generate_cycle_update(); \
generate_branch_no_cycle_update(writeback_location, new_pc) \
#define generate_conditional_branch(ireg_a, ireg_b, type, writeback_location) \
generate_branch_filler_##type(ireg_a, ireg_b, writeback_location) \
// a0 holds the destination
#define generate_indirect_branch_cycle_update(type) \