Fix and reenable Android arm 32 bit builds

Removed the last bits of text relocations by moving all relevant RAMs to
the stub reachable area. This should be as fast or even faster than
previous code.

.gitlab-ci.yml

@@ -141,6 +141,12 @@ libretro-build-osx-arm64:
     - .core-defs
 
 ################################### CELLULAR #################################
+# Android ARMv7a
+android-armeabi-v7a:
+  extends:
+    - .libretro-android-jni-armeabi-v7a
+    - .core-defs
+
 # Android ARMv8a
 android-arm64-v8a:
   extends:

arm/arm_emit.h

@@ -1980,4 +1980,9 @@ void init_emitter(void) {
   memcpy(ldst_lookup_tables, ldst_handler_functions, sizeof(ldst_lookup_tables));
 }
 
+u32 execute_arm_translate_internal(u32 cycles, void *regptr);
+u32 function_cc execute_arm_translate(u32 cycles) {
+  return execute_arm_translate_internal(cycles, &reg[0]);
+}
+
 #endif

arm/arm_stub.S

@@ -72,10 +72,12 @@ _##symbol:
 #define EWRAM_OFF      -0x80000
 #define SPSR_RAM_OFF      0x100
 #define REGMODE_RAM_OFF   0x118
-#define OAM_RAM_OFF       0x200
-#define PAL_RAM_OFF       0x600
-#define STORE_TBL_OFF     0xA00
-#define RDMAP_OFF         0xC40
+#define STORE_TBL_OFF     0x1DC
+#define OAM_RAM_OFF       0x500
+#define PAL_RAM_OFF       0x900
+#define RDMAP_OFF         0xD00
+#define IOREG_OFF        0x8D00
+
 
 #define extract_u16(rd, rs) \
   uxth rd, rs
@@ -453,12 +455,12 @@ execute_swi_function_builder(div, thumb)
 
 @ Uses sp as reg_base; must hold consistently true.
 
-defsymbl(execute_arm_translate)
+defsymbl(execute_arm_translate_internal)
 
   @ save the registers to be able to return later
   stmdb sp!, { r4, r5, r6, r7, r8, r9, r10, r11, r12, lr }
 
-  ldr reg_base, =reg                      @ init base_reg
+  mov reg_base, r1                        @ init base_reg
 
   mvn reg_cycles, r0                      @ load cycle counter
 
@@ -801,7 +803,7 @@ ld_iwram_##load_type:                     /* IWRAM area                    */;\
   add pc, lr, #4                                                             ;\
                                                                              ;\
 ld_ioram_##load_type:                     /* I/O RAM area                  */;\
-  ldr  r2, =io_registers                                                     ;\
+  add r2, reg_base, #IOREG_OFF                                               ;\
   exec_ld_op_##load_type(10)              /* Clear upper bits (10 LSB)     */;\
   add pc, lr, #4                                                             ;\
                                                                              ;\
@@ -891,17 +893,19 @@ defsymbl(spsr)
   .space 24
 defsymbl(reg_mode)
   .space 196
-  .space 36    @ Padding for alignment
-defsymbl(oam_ram)
-  .space 0x400
-defsymbl(palette_ram)
-  .space 0x400
 @ Place lookup tables here for easy access via base_reg too
 defsymbl(ldst_lookup_tables)
   .space 4*16*4   @ store
   .space 5*16*4   @ loads
+  .space 228      @ Padding for alignment
+defsymbl(oam_ram)
+  .space 0x400
+defsymbl(palette_ram)
+  .space 0x400
 defsymbl(memory_map_read)
   .space 0x8000
+defsymbl(io_registers)
+  .space 0x400
 
 defsymbl(palette_ram_converted)
   .space 0x400

cpu.c

@@ -1614,6 +1614,7 @@ u16 palette_ram_converted[512];
 u8 ewram[1024 * 256 * 2];
 u8 iwram[1024 * 32 * 2];
 u8 vram[1024 * 96];
+u16 io_registers[512];
 #endif
 
 void execute_arm(u32 cycles)

gba_memory.c

@@ -308,7 +308,6 @@ u32 gamepak_waitstate_sequential[2][3][3] =
   }
 };
 
-u16 io_registers[512];
 u8 bios_rom[1024 * 16];
 u32 bios_read_protect;
 

psp/mips_stub.S

@@ -618,6 +618,8 @@ defsymbl(vram)
   .space 0x18000
 defsymbl(ewram)
   .space 0x80000
+defsymbl(io_registers)
+  .space 0x400
 
 .data
 .align 6

x86/x86_stub.S

@@ -551,6 +551,8 @@ defsymbl(vram)
   .space 0x18000
 defsymbl(ewram)
   .space 0x80000
+defsymbl(io_registers)
+  .space 0x400
 
 defsymbl(spsr)
   .space 24