Partially revert 71ebc49b
Just move the complex lookup to C for simplicity since there's not a lot of gain to have. This makes it easier for devices with weird jit caches.
This commit is contained in:
David Guillen Fandos
parent
84cd7b2934
commit
221b8ff115
195
arm/arm_stub.S
195
arm/arm_stub.S
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@ -2,6 +2,7 @@
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#include "../gpsp_config.h"
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#define defsymbl(symbol) \
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.align 2; \
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.type symbol, %function ;\
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.global symbol ; \
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.global _##symbol ; \
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@ -148,82 +149,6 @@ _##symbol:
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bl function ;\
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ldmia sp!, { call_c_saved_regs } ;\
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@ Jumps to PC (ARM or Thumb modes)
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@ This is really two functions/routines in one
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@ r0 contains the PC
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.align 2
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#define execute_pc_builder(mode, align) ;\
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defsymbl(arm_indirect_branch_##mode) ;\
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save_flags() ;\
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execute_pc_##mode: ;\
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bic r0, r0, #(align) /* Align PC */;\
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mov r1, r0, lsr #24 /* Get region */;\
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ldr pc, [pc, r1, lsl #2] ;\
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nop ;\
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.long 3f /* 0 BIOS (like ROM) */;\
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.long 3f /* 1 Bad region */;\
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.long 1f /* 2 EWRAM */;\
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.long 2f /* 3 IWRAM */;\
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.long 3f /* 4 Not supported */;\
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.long 3f /* 5 Not supported */;\
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.long 3f /* 6 Not supported */;\
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.long 3f /* 7 Not supported */;\
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.long 3f /* 8 ROM */;\
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.long 3f /* 9 ROM */;\
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.long 3f /* A ROM */;\
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.long 3f /* B ROM */;\
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.long 3f /* C ROM */;\
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.long 3f /* D ROM */;\
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.long 3f /* E ROM */;\
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.long 3f /* F Bad region */;\
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;\
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3: ;\
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/* r0 already contains the PC to jump to */ ;\
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call_c_function(block_lookup_address_##mode) ;\
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restore_flags() ;\
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bx r0 ;\
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1: ;\
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ldr r1, =(ewram+0x40000) /* Load base addr */;\
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mov r2, r0, lsl #14 /* addr &= 0x3ffff */;\
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mov r2, r2, lsr #14 ;\
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ldrh r2, [r1, r2] /* Load half word there */;\
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ldr r1, =(ram_translation_cache) ;\
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subs r2, #0x0104 /* Check valid tag + rebase */;\
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ble 3b /* Data/non-entry code -> transl.*/;\
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mov r2, r2, lsr #1 /* Ignores LSB */;\
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restore_flags() ;\
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add pc, r1, r2, lsl #4 /* Offset is 16 byte aligned */;\
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2: ;\
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ldr r1, =(iwram) /* Load base addr */;\
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mov r2, r0, lsl #17 /* addr &= 0x7fff */;\
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mov r2, r2, lsr #17 ;\
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ldrh r2, [r1, r2] /* Load half word there */;\
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ldr r1, =(ram_translation_cache) ;\
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subs r2, #0x0104 /* Check valid tag + rebase */;\
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ble 3b /* Data/non-entry code -> transl.*/;\
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mov r2, r2, lsr #1 /* Ignores LSB */;\
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restore_flags() ;\
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add pc, r1, r2, lsl #4 /* Offset is 16 byte aligned */;\
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.size arm_indirect_branch_##mode, .-arm_indirect_branch_##mode
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execute_pc_builder(arm, 0x3)
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execute_pc_builder(thumb, 0x1)
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@ Resumes execution from saved PC, in any mode
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execute_pc:
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ldr r0, [reg_base, #REG_PC] @ load new PC
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ldr r1, [reg_base, #REG_CPSR] @ r1 = flags
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tst r1, #0x20 @ see if Thumb bit is set
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bne 2f
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load_registers_arm()
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b execute_pc_arm
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2:
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load_registers_thumb()
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b execute_pc_thumb
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@ Update the GBA hardware (video, sound, input, etc)
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@ -245,7 +170,6 @@ execute_pc:
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#define arm_update_gba_builder(name, mode, return_op) ;\
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;\
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.align 2 ;\
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defsymbl(arm_update_gba_##name) ;\
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load_pc_##return_op() ;\
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str r0, [reg_base, #REG_PC] /* write out the PC */;\
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@ -269,12 +193,28 @@ wait_halt_##name: ;\
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;\
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ldr r0, [reg_base, #CHANGED_PC_STATUS] /* load PC changed status */;\
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cmp r0, #0 /* see if PC has changed */;\
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bne execute_pc /* go jump/translate */;\
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bne 1f /* go jump/translate */;\
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;\
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load_registers_##mode() /* reload registers */;\
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restore_flags() ;\
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return_##return_op() /* continue, no PC change */;\
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.size arm_update_gba_##mode, .-arm_update_gba_##mode
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;\
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1: ;\
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ldr r1, [reg_base, #REG_CPSR] /* r1 = flags */;\
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ldr r0, [reg_base, #REG_PC] /* load new PC */;\
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tst r1, #0x20 /* see if Thumb bit is set */;\
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bne 2f /* if so load Thumb PC */;\
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;\
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load_registers_arm() /* load ARM regs */;\
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call_c_function(block_lookup_address_arm) ;\
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restore_flags() ;\
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bx r0 /* jump to new ARM block */;\
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2: ;\
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load_registers_thumb() /* load Thumb regs */;\
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call_c_function(block_lookup_address_thumb) ;\
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restore_flags() ;\
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bx r0 /* jump to new ARM block */;\
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.size arm_update_gba_##name, .-arm_update_gba_##name
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arm_update_gba_builder(arm, arm, straight)
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arm_update_gba_builder(thumb, thumb, straight)
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@ -306,33 +246,52 @@ cheat_hook_builder(thumb)
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@ Input:
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@ r0: PC to branch to
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.align 2
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defsymbl(arm_indirect_branch_arm)
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save_flags()
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0
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defsymbl(arm_indirect_branch_thumb)
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save_flags()
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0
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defsymbl(arm_indirect_branch_dual_arm)
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save_flags()
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tst r0, #0x01 @ check lower bit
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beq execute_pc_arm @ Keep executing ARM code
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bic r0, r0, #0x01 @ Switch to Thumb mode
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bne 1f @ if set going to Thumb mode
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0 @ keep executing arm code
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1:
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store_registers_arm() @ save out ARM registers
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load_registers_thumb() @ load in Thumb registers
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ldr r1, [reg_base, #REG_CPSR] @ load cpsr
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load_registers_thumb() @ load in Thumb registers
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orr r1, r1, #0x20 @ set Thumb mode
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str r1, [reg_base, #REG_CPSR] @ store flags
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b execute_pc_thumb @ Now execute Thumb
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0
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.size arm_indirect_branch_dual_arm, .-arm_indirect_branch_dual_arm
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.align 2
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defsymbl(arm_indirect_branch_dual_thumb)
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save_flags()
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tst r0, #0x01 @ check lower bit
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bne execute_pc_thumb @ Keep executing Thumb mode
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beq 1f @ if set going to ARM mode
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0 @ keep executing thumb code
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1:
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store_registers_thumb() @ save out Thumb registers
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load_registers_arm() @ load in ARM registers
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ldr r1, [reg_base, #REG_CPSR] @ load cpsr
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load_registers_arm() @ load in ARM registers
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bic r1, r1, #0x20 @ clear Thumb mode
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str r1, [reg_base, #REG_CPSR] @ store flags
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b execute_pc_arm @ Now execute ARM
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0
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.size arm_indirect_branch_dual_thumb, .-arm_indirect_branch_dual_thumb
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@ Update the cpsr.
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@ -342,7 +301,6 @@ defsymbl(arm_indirect_branch_dual_thumb)
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@ r1: bitmask of which bits in cpsr to update
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@ r2: current PC
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.align 2
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defsymbl(execute_store_cpsr)
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save_flags()
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and reg_flags, r0, r1 @ reg_flags = new_cpsr & store_mask
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@ -358,13 +316,15 @@ defsymbl(execute_store_cpsr)
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load_registers_arm() @ restore ARM registers
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cmp r0, #0 @ check new PC
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beq 1f @ if it's zero, return
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bne 1f @ if it's zero, resume
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b execute_pc_arm
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1:
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restore_flags()
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add pc, lr, #4 @ return
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1:
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0 @ return to PC ARM address
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.size execute_store_cpsr, .-execute_store_cpsr
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@ Update the current spsr.
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@ -373,7 +333,6 @@ defsymbl(execute_store_cpsr)
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@ r0: new cpsr value
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@ r1: bitmask of which bits in spsr to update
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.align 2
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defsymbl(execute_store_spsr)
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ldr r1, =spsr @ r1 = spsr
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ldr r2, [reg_base, #CPU_MODE] @ r2 = CPU_MODE
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@ -386,7 +345,6 @@ defsymbl(execute_store_spsr)
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@ Output:
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@ r0: spsr
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.align 2
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defsymbl(execute_read_spsr)
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ldr r0, =spsr @ r0 = spsr
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ldr r1, [reg_base, #CPU_MODE] @ r1 = CPU_MODE
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@ -399,7 +357,6 @@ defsymbl(execute_read_spsr)
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@ Input:
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@ r0: current pc
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.align 2
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defsymbl(execute_spsr_restore)
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save_flags()
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ldr r1, =spsr @ r1 = spsr
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@ -417,11 +374,15 @@ defsymbl(execute_spsr_restore)
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bne 2f @ if so handle it
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load_registers_arm() @ restore ARM registers
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b execute_pc_arm
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0
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2:
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load_registers_thumb() @ load Thumb registers
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b execute_pc_thumb
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0
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@ Setup the mode transition work for calling an SWI.
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@ -431,7 +392,6 @@ defsymbl(execute_spsr_restore)
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#define execute_swi_builder(mode) ;\
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;\
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.align 2 ;\
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defsymbl(execute_swi_##mode) ;\
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save_flags() ;\
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ldr r1, =reg_mode /* r1 = reg_mode */;\
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@ -463,7 +423,6 @@ execute_swi_builder(thumb)
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#define execute_swi_function_builder(swi_function, mode) ;\
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;\
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.align 2 ;\
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defsymbl(execute_swi_hle_##swi_function##_##mode) ;\
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save_flags() ;\
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store_registers_##mode() ;\
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@ -485,7 +444,6 @@ execute_swi_function_builder(div, thumb)
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@ Uses sp as reg_base; must hold consistently true.
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.align 2
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defsymbl(execute_arm_translate)
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@ save the registers to be able to return later
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@ -607,7 +565,6 @@ ext_store_ignore:
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#define execute_store_builder(store_type, store_op, store_op16, load_op, tn) ;\
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;\
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.align 2 ;\
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defsymbl(execute_store_u##store_type) ;\
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execute_store_body(store_type, tn) ;\
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;\
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@ -749,7 +706,21 @@ alert_loop:
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bne alert_loop @ Keep looping until it is
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mvn reg_cycles, r0 @ load new cycle count
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b execute_pc @ restart execution at PC
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ldr r0, [reg_base, #REG_PC] @ load new PC
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ldr r1, [reg_base, #REG_CPSR] @ r1 = flags
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tst r1, #0x20 @ see if Thumb bit is set
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bne 2f
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load_registers_arm()
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0 @ jump to new ARM block
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2:
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load_registers_thumb()
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0 @ jump to new Thumb block
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4:
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restore_flags()
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@ -763,8 +734,17 @@ lookup_pc:
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ldr r0, [reg_base, #REG_PC] @ r0 = new pc
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ldr r1, [reg_base, #REG_CPSR] @ r1 = flags
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tst r1, #0x20 @ see if Thumb bit is set
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beq execute_pc_arm @ if not lookup ARM
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b execute_pc_thumb
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beq lookup_pc_arm @ if not lookup ARM
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lookup_pc_thumb:
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0 @ jump to new Thumb block
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lookup_pc_arm:
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0 @ jump to new ARM block
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#define sign_extend_u8(reg)
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@ -801,7 +781,6 @@ lookup_pc:
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#define execute_load_builder(load_type, load_function, load_op, mask) ;\
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;\
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.align 2 ;\
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defsymbl(execute_load_##load_type) ;\
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save_flags() ;\
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tst r0, mask /* make sure address is in range */;\
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