lifning
/
gpsp
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Rearrange register layout and exclude useless regs from savestat 

This changes the savestate format once again.
This commit is contained in:
David Guillen Fandos 2021-08-15 21:07:20 +02:00
parent 2d34d91c64
commit 5be5015338
7 changed files with 68 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arm/arm_emit.h
View File

@ -111,7 +111,6 @@ void execute_store_u32_safe(u32 address, u32 source);
#define reg_x5 ARMREG_R8
#define mem_reg (~0U)
#define save1_reg 21
/*
@ -1462,14 +1461,14 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
arm_block_memory_offset_##offset_type(); \
arm_block_memory_writeback_##access_type(writeback_type); \
ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \
arm_generate_store_reg(reg_s0, save1_reg); \
arm_generate_store_reg(reg_s0, REG_SAVE); \
\
for(i = 0; i < 16; i++) \
{ \
if((reg_list >> i) & 0x01) \
{ \
cycle_count++; \
arm_generate_load_reg(reg_s0, save1_reg); \
arm_generate_load_reg(reg_s0, REG_SAVE); \
generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \
if(reg_list & ~((2 << i) - 1)) \
{ \
@ -1735,14 +1734,14 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
#define thumb_block_memory_extra_down() \
#define thumb_block_memory_extra_pop_pc() \
thumb_generate_load_reg(reg_s0, save1_reg); \
thumb_generate_load_reg(reg_s0, REG_SAVE); \
generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
generate_function_call(execute_load_u32); \
write32((pc + 4)); \
generate_indirect_branch_cycle_update(thumb) \
#define thumb_block_memory_extra_push_lr(base_reg) \
thumb_generate_load_reg(reg_s0, save1_reg); \
thumb_generate_load_reg(reg_s0, REG_SAVE); \
generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
thumb_generate_load_reg(reg_a1, REG_LR); \
generate_function_call(execute_store_u32_safe) \
@ -1789,14 +1788,14 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \
thumb_block_address_preadjust_##pre_op(); \
thumb_block_address_postadjust_##post_op(base_reg); \
thumb_generate_store_reg(reg_s0, save1_reg); \
thumb_generate_store_reg(reg_s0, REG_SAVE); \
\
for(i = 0; i < 8; i++) \
{ \
if((reg_list >> i) & 0x01) \
{ \
cycle_count++; \
thumb_generate_load_reg(reg_s0, save1_reg); \
thumb_generate_load_reg(reg_s0, REG_SAVE); \
generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \
if(reg_list & ~((2 << i) - 1)) \
{ \

19
arm/arm_stub.S
View File

@ -36,16 +36,17 @@ _##symbol:
#define REG_C_FLAG (18 * 4)
#define REG_V_FLAG (19 * 4)
#define REG_CPSR (20 * 4)
#define CPU_MODE (21 * 4)
#define CPU_HALT_STATE (22 * 4)
#define REG_SAVE (21 * 4)
#define REG_SAVE2 (22 * 4)
#define REG_SAVE3 (23 * 4)
#define CPU_MODE (29 * 4)
#define CPU_HALT_STATE (30 * 4)
#define CHANGED_PC_STATUS (31 * 4)
#define COMPLETED_FRAME (32 * 4)
#define OAM_UPDATED (33 * 4)
#define CHANGED_PC_STATUS (24 * 4)
#define COMPLETED_FRAME (25 * 4)
#define OAM_UPDATED (26 * 4)
#define REG_SAVE (27 * 4)
#define REG_SAVE2 (28 * 4)
#define REG_SAVE3 (29 * 4)
#define REG_SAVE4 (30 * 4)
#define REG_SAVE5 (31 * 4)
#define reg_a0 r0
#define reg_a1 r1

12
cpu.c
View File

@ -3780,12 +3780,12 @@ void init_cpu(void)
reg_mode[MODE_SUPERVISOR][5] = 0x03007FE0;
}
#define cpu_savestate_builder(type) \
void cpu_##type##_savestate(void) \
{ \
state_mem_##type(reg, 0x100); \
state_mem_##type##_array(spsr); \
state_mem_##type##_array(reg_mode); \
#define cpu_savestate_builder(type) \
void cpu_##type##_savestate(void) \
{ \
state_mem_##type(reg, 4 * REG_IGNORE); \
state_mem_##type##_array(spsr); \
state_mem_##type##_array(reg_mode); \
}
cpu_savestate_builder(read)

25
cpu.h
View File

@ -69,6 +69,7 @@ typedef u16 irq_type;
typedef enum
{
// CPU status & registers
REG_SP = 13,
REG_LR = 14,
REG_PC = 15,
@ -77,14 +78,22 @@ typedef enum
REG_C_FLAG = 18,
REG_V_FLAG = 19,
REG_CPSR = 20,
REG_SAVE = 21,
REG_SAVE2 = 22,
REG_SAVE3 = 23,
CPU_MODE = 29,
CPU_HALT_STATE = 30,
CHANGED_PC_STATUS = 31,
COMPLETED_FRAME = 32,
OAM_UPDATED = 33
CPU_MODE = 21,
CPU_HALT_STATE = 22,
REG_IGNORE = 23,
// Dynarec signaling and spilling
// (Not really part of the CPU state)
CHANGED_PC_STATUS = 24,
COMPLETED_FRAME = 25,
OAM_UPDATED = 26,
REG_SAVE = 27,
REG_SAVE2 = 28,
REG_SAVE3 = 29,
REG_SAVE4 = 30,
REG_SAVE5 = 31,
REG_MAX = 64
} ext_reg_numbers;
typedef enum

14
psp/mips_emit.h
View File

@ -2513,13 +2513,13 @@ u8 swi_hle_handle[256] =
// Register save layout as follows:
#define ReOff_RegPC (15*4) // REG_PC
#define ReOff_CPSR (20*4) // REG_CPSR
#define ReOff_SaveR1 (21*4) // 3 save scratch regs
#define ReOff_SaveR2 (22*4)
#define ReOff_SaveR3 (23*4)
#define ReOff_OamUpd (33*4) // OAM_UPDATED
#define ReOff_GP_Save (34*4) // GP_SAVE
#define ReOff_RegPC (REG_PC * 4) // REG_PC
#define ReOff_CPSR (REG_CPSR * 4) // REG_CPSR
#define ReOff_SaveR1 (REG_SAVE * 4) // 3 save scratch regs
#define ReOff_SaveR2 (REG_SAVE2 * 4)
#define ReOff_SaveR3 (REG_SAVE3 * 4)
#define ReOff_OamUpd (OAM_UPDATED*4) // OAM_UPDATED
#define ReOff_GP_Save (REG_SAVE4 * 4) // GP_SAVE
// Saves all regs to their right slot and loads gp
#define emit_save_regs(save_a2) { \

21
psp/mips_stub.S
View File

@ -100,16 +100,17 @@ symbol:
.equ REG_C_FLAG, (18 * 4)
.equ REG_V_FLAG, (19 * 4)
.equ REG_CPSR, (20 * 4)
.equ REG_SAVE, (21 * 4)
.equ REG_SAVE2, (22 * 4)
.equ REG_SAVE3, (23 * 4)
.equ CPU_MODE, (29 * 4)
.equ CPU_HALT_STATE, (30 * 4)
.equ CHANGED_PC_STATUS, (31 * 4)
.equ COMPLETED_FRAME, (32 * 4)
.equ OAM_UPDATED, (33 * 4)
.equ GP_SAVE, (34 * 4)
.equ GP_SAVE_HI, (35 * 4)
.equ CPU_MODE, (21 * 4)
.equ CPU_HALT_STATE, (22 * 4)
.equ CHANGED_PC_STATUS, (24 * 4)
.equ COMPLETED_FRAME, (25 * 4)
.equ OAM_UPDATED, (26 * 4)
.equ REG_SAVE, (27 * 4)
.equ REG_SAVE2, (28 * 4)
.equ REG_SAVE3, (29 * 4)
.equ GP_SAVE, (30 * 4)
.equ GP_SAVE_HI, (31 * 4)
.equ SPSR_BASE, (0x100 + 0x400 * 3)
.equ REGMODE_BASE, (SPSR_BASE + 24)

19
x86/x86_stub.S
View File

@ -52,14 +52,17 @@ _##symbol:
.equ REG_C_FLAG, (18 * 4)
.equ REG_V_FLAG, (19 * 4)
.equ REG_CPSR, (20 * 4)
.equ REG_SAVE, (21 * 4)
.equ REG_SAVE2, (22 * 4)
.equ REG_SAVE3, (23 * 4)
.equ CPU_MODE, (29 * 4)
.equ CPU_HALT_STATE, (30 * 4)
.equ CHANGED_PC_STATUS, (31 * 4)
.equ COMPLETED_FRAME, (32 * 4)
.equ OAM_UPDATED, (33 * 4)
.equ CPU_MODE, (21 * 4)
.equ CPU_HALT_STATE, (22 * 4)
.equ CHANGED_PC_STATUS, (24 * 4)
.equ COMPLETED_FRAME, (25 * 4)
.equ OAM_UPDATED, (26 * 4)
.equ REG_SAVE, (27 * 4)
.equ REG_SAVE2, (28 * 4)
.equ REG_SAVE3, (29 * 4)
.equ REG_SAVE4, (30 * 4)
.equ REG_SAVE5, (31 * 4)
.equ ESTORE_U32_TBL, -(16 * 4)
.equ ESTORE_U16_TBL, -(32 * 4)