[ARM] Rework memory handlers for speed amb simplicity
This removes one branch and emits the region selection code directly in the JIT cache. Trading memory for speed (although it's not a big improvement). This is a step towards enabling MMAP caches in ARM (due to the 32MB offset limitation in branches).
This commit is contained in:
David Guillen Fandos
parent
4bebb6135d
commit
d558fb4fc4
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@ -1378,6 +1378,12 @@ typedef struct {
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(1 << 25) | \
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ARM_DEF_COND(cond)
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#define ARM_USAT_ASR(p, rd, sat, rm, sa, cond) \
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ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm) | 0x10, 2, sa, rd, sat, 0, 0x37, cond))
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#define ARM_USAT_LSL(p, rd, sat, rm, sa, cond) \
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ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm) | 0x10, 0, sa, rd, sat, 0, 0x37, cond))
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typedef union {
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ARMInstrBR br;
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@ -51,8 +51,6 @@ u32 execute_spsr_restore(u32 address);
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void execute_swi_arm(u32 pc);
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void execute_swi_thumb(u32 pc);
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void execute_store_u32_safe(u32 address, u32 source);
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#define STORE_TBL_OFF 0x1DC
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#define SPSR_RAM_OFF 0x100
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@ -1271,16 +1269,46 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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* (same with the stores)
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*/
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#define generate_load_call_byte(tblnum) \
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ARM_USAT_ASR(0, reg_a1, 4, reg_a0, 24, ARMCOND_AL); \
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generate_add_imm(reg_a1, (STORE_TBL_OFF + 64*tblnum) >> 2, 0); \
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ARM_LDR_REG_REG_SHIFT(0, reg_a1, reg_base, reg_a1, 0, 2); \
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ARM_BLX(0, reg_a1); \
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#define generate_load_call_mbyte(tblnum, abits) \
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ARM_MOV_REG_IMMSHIFT(0, reg_a1, reg_a0, ARMSHIFT_ROR, abits) \
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ARM_USAT_ASR(0, reg_a1, 4, reg_a1, 24-abits, ARMCOND_AL); \
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generate_add_imm(reg_a1, (STORE_TBL_OFF + 64*tblnum) >> 2, 0); \
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ARM_LDR_REG_REG_SHIFT(0, reg_a1, reg_base, reg_a1, 0, 2); \
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ARM_BLX(0, reg_a1); \
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#define generate_store_call(tblnum) \
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ARM_USAT_ASR(0, reg_a2, 4, reg_a0, 24, ARMCOND_AL); \
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generate_add_imm(reg_a2, (STORE_TBL_OFF + 64*tblnum) >> 2, 0); \
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ARM_LDR_REG_REG_SHIFT(0, reg_a2, reg_base, reg_a2, 0, 2); \
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ARM_BLX(0, reg_a2); \
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#define generate_store_call_u8() generate_store_call(0)
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#define generate_store_call_u16() generate_store_call(1)
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#define generate_store_call_u32() generate_store_call(2)
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#define generate_store_call_u32_safe() generate_store_call(3)
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#define generate_load_call_u8() generate_load_call_byte(4)
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#define generate_load_call_s8() generate_load_call_byte(5)
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#define generate_load_call_u16() generate_load_call_mbyte(6, 1)
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#define generate_load_call_s16() generate_load_call_mbyte(7, 1)
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#define generate_load_call_u32() generate_load_call_mbyte(8, 2)
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#define arm_access_memory_load(mem_type) \
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cycle_count += 2; \
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generate_function_call(execute_load_##mem_type); \
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generate_load_call_##mem_type(); \
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write32((pc + 8)); \
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arm_generate_store_reg_pc_no_flags(reg_rv, rd) \
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#define arm_access_memory_store(mem_type) \
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cycle_count++; \
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arm_generate_load_reg_pc(reg_a1, rd, 12); \
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generate_function_call(execute_store_##mem_type); \
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generate_store_call_##mem_type(); \
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write32((pc + 4)) \
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/* Calculate the address into a0 from _rn, _rm */
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@ -1384,20 +1412,20 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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/* TODO: Make these use cached registers. Implement iwram_stack_optimize. */
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#define arm_block_memory_load() \
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generate_function_call(execute_load_u32); \
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generate_load_call_u32(); \
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write32((pc + 8)); \
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arm_generate_store_reg(reg_rv, i) \
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#define arm_block_memory_store() \
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arm_generate_load_reg_pc(reg_a1, i, 8); \
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generate_function_call(execute_store_u32_safe) \
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generate_store_call_u32_safe() \
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#define arm_block_memory_final_load() \
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arm_block_memory_load() \
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#define arm_block_memory_final_store() \
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arm_generate_load_reg_pc(reg_a1, i, 12); \
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generate_function_call(execute_store_u32); \
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generate_store_call_u32(); \
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write32((pc + 4)) \
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#define arm_block_memory_adjust_pc_store() \
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@ -1482,13 +1510,13 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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arm_decode_swap(); \
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cycle_count += 3; \
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arm_generate_load_reg(reg_a0, rn); \
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generate_function_call(execute_load_##type); \
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generate_load_call_##type(); \
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write32((pc + 8)); \
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generate_mov(reg_a2, reg_rv); \
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arm_generate_load_reg(reg_a0, rn); \
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arm_generate_load_reg(reg_a1, rm); \
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arm_generate_store_reg(reg_a2, rd); \
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generate_function_call(execute_store_##type); \
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generate_store_call_##type(); \
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write32((pc + 4)); \
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} \
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@ -1651,14 +1679,14 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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#define thumb_access_memory_load(mem_type, _rd) \
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cycle_count += 2; \
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generate_function_call(execute_load_##mem_type); \
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generate_load_call_##mem_type(); \
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write32((pc + 4)); \
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thumb_generate_store_reg(reg_rv, _rd) \
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#define thumb_access_memory_store(mem_type, _rd) \
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cycle_count++; \
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thumb_generate_load_reg(reg_a1, _rd); \
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generate_function_call(execute_store_##mem_type); \
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generate_store_call_##mem_type(); \
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write32((pc + 2)) \
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#define thumb_access_memory_generate_address_pc_relative(offset, _rb, _ro) \
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@ -1727,7 +1755,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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#define thumb_block_memory_extra_pop_pc() \
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thumb_generate_load_reg(reg_s0, REG_SAVE); \
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generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
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generate_function_call(execute_load_u32); \
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generate_load_call_u32(); \
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write32((pc + 4)); \
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generate_indirect_branch_cycle_update(thumb) \
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@ -1735,23 +1763,23 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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thumb_generate_load_reg(reg_s0, REG_SAVE); \
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generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
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thumb_generate_load_reg(reg_a1, REG_LR); \
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generate_function_call(execute_store_u32_safe) \
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generate_store_call_u32_safe()
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#define thumb_block_memory_load() \
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generate_function_call(execute_load_u32); \
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generate_load_call_u32(); \
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write32((pc + 4)); \
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thumb_generate_store_reg(reg_rv, i) \
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#define thumb_block_memory_store() \
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thumb_generate_load_reg(reg_a1, i); \
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generate_function_call(execute_store_u32_safe) \
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generate_store_call_u32_safe()
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#define thumb_block_memory_final_load() \
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thumb_block_memory_load() \
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#define thumb_block_memory_final_store() \
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thumb_generate_load_reg(reg_a1, i); \
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generate_function_call(execute_store_u32); \
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generate_store_call_u32(); \
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write32((pc + 2)) \
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#define thumb_block_memory_final_no(access_type) \
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@ -94,12 +94,7 @@ _##symbol:
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ldr reg_x5, [reg_base, #REG_R14] ;\
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#define load_registers_thumb() ;\
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ldr reg_x0, [reg_base, #REG_R0] ;\
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ldr reg_x1, [reg_base, #REG_R1] ;\
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ldr reg_x2, [reg_base, #REG_R2] ;\
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ldr reg_x3, [reg_base, #REG_R3] ;\
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ldr reg_x4, [reg_base, #REG_R4] ;\
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ldr reg_x5, [reg_base, #REG_R5] ;\
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ldm reg_base, {reg_x0, reg_x1, reg_x2, reg_x3, reg_x4, reg_x5}
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@ Will store the register set from cached registers back to memory.
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@ -113,12 +108,7 @@ _##symbol:
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str reg_x5, [reg_base, #REG_R14] ;\
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#define store_registers_thumb() ;\
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str reg_x0, [reg_base, #REG_R0] ;\
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str reg_x1, [reg_base, #REG_R1] ;\
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str reg_x2, [reg_base, #REG_R2] ;\
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str reg_x3, [reg_base, #REG_R3] ;\
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str reg_x4, [reg_base, #REG_R4] ;\
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str reg_x5, [reg_base, #REG_R5] ;\
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stm reg_base, {reg_x0, reg_x1, reg_x2, reg_x3, reg_x4, reg_x5}
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@ Returns an updated persistent cpsr with the cached flags register.
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@ -512,12 +502,6 @@ return_to_main:
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#define execute_store_builder(store_type, str_op, str_op16, load_op, tnum) ;\
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;\
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defsymbl(execute_store_u##store_type) ;\
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usat r2, #4, r0, asr #24 /* r2 contains [0-15] */;\
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add r2, r2, #((STORE_TBL_OFF + 16*4*tnum) >> 2) /* add table offset */;\
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ldr pc, [reg_base, r2, lsl #2] /* load handler addr */;\
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nop ;\
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;\
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ext_store_u##store_type: ;\
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save_flags() ;\
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ldr r2, [lr] /* load PC */;\
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@ -571,7 +555,6 @@ ext_store_oam_ram_u##store_type: ;\
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ldr r0, [lr] /* load PC */;\
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str r0, [reg_base, #REG_PC] /* write out PC */;\
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b smc_write /* perform smc write */;\
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.size execute_store_u##store_type, .-execute_store_u##store_type
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@ for ignored areas, just return
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ext_store_ignore:
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@ -601,12 +584,6 @@ execute_store_builder(32, str, str, ldr, 2)
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@ This is a store that is executed in a strm case (so no SMC checks in-between)
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defsymbl(execute_store_u32_safe)
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usat r2, #4, r0, asr #24
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add r2, r2, #((STORE_TBL_OFF + 16*4*3) >> 2)
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ldr pc, [reg_base, r2, lsl #2]
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nop
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ext_store_u32_safe:
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str lr, [reg_base, #REG_SAVE3] @ Restore lr
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save_flags()
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@ -642,7 +619,6 @@ ext_store_oam_ram_u32_safe:
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str r1, [r0, r2] @ store data
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str r2, [reg_base, #OAM_UPDATED] @ store anything non zero here
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bx lr @ Return
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.size execute_store_u32_safe, .-execute_store_u32_safe
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write_epilogue:
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@ -744,17 +720,6 @@ lookup_pc_arm:
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#define execute_load_builder(load_type, albits, load_function, tnum) ;\
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;\
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defsymbl(execute_load_##load_type) ;\
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.if albits >= 1 ;\
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ror r1, r0, #(albits) /* move alignment bits to MSB */;\
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usat r1, #4, r1, asr #(24-albits) /* r1 contains [0-15] */;\
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.else ;\
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usat r1, #4, r0, asr #24 /* r1 contains [0-15] */;\
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.endif ;\
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add r1, r1, #((STORE_TBL_OFF + 16*4*tnum) >> 2) /* add table offset */;\
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ldr pc, [reg_base, r1, lsl #2] /* load handler addr */;\
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nop ;\
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;\
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ld_bios_##load_type: /* BIOS area, need to verify PC */;\
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save_flags() ;\
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ldr r1, [lr] /* r1 = PC */;\
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@ -809,8 +774,7 @@ ld_slow_##load_type: ;\
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call_c_function(load_function) ;\
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restore_flags() ;\
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add pc, lr, #4 /* return */;\
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;\
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.size execute_load_##load_type, .-execute_load_##load_type
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#define load_table_gen(load_type) ;\
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.long ld_bios_##load_type /* 0 BIOS */;\
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