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Minor unused stuff cleanup

This commit is contained in:
David Guillen Fandos 2021-11-06 21:49:08 +01:00
parent c0804fa48d
commit 92180d5d7e
3 changed files with 0 additions and 54 deletions
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6
arm/arm_emit.h
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@ -1448,12 +1448,6 @@ static void trace_instruction(u32 pc, u32 mode)
#define word_bit_count(word) \
(bit_count[word >> 8] + bit_count[word & 0xFF]) \
#define sprint_no(access_type, pre_op, post_op, wb) \
#define sprint_yes(access_type, pre_op, post_op, wb) \
printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \
/* TODO: Make these use cached registers. Implement iwram_stack_optimize. */
#define arm_block_memory_load() \

5
cpu.c
View File

@ -1096,11 +1096,6 @@ const u32 psr_masks[16] =
#define word_bit_count(word) \
(bit_count[word >> 8] + bit_count[word & 0xFF]) \
#define sprint_no(access_type, offset_type, writeback_type) \
#define sprint_yes(access_type, offset_type, writeback_type) \
printf("sbit on %s %s %s\n", #access_type, #offset_type, #writeback_type) \
#define arm_block_writeback_load() \
if(!((reg_list >> rn) & 0x01)) \
{ \

43
mips/mips_emit.h
View File

@ -1395,11 +1395,6 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
#define word_bit_count(word) \
(bit_count[word >> 8] + bit_count[word & 0xFF]) \
#define sprint_no(access_type, pre_op, post_op, wb) \
#define sprint_yes(access_type, pre_op, post_op, wb) \
printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \
#define arm_block_memory_load() \
generate_function_call_swap_delay(execute_aligned_load32); \
generate_store_reg(reg_rv, i) \
@ -1529,44 +1524,6 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
} \
} \
#define arm_block_writeback_no()
#define arm_block_writeback_yes() \
mips_emit_addu(arm_to_mips_reg[rn], reg_a2, reg_zero) \
#define arm_block_address_preadjust_up_full(wb) \
mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], \
((word_bit_count(reg_list)) * 4)); \
arm_block_writeback_##wb() \
#define arm_block_address_preadjust_up(wb) \
mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], 4); \
arm_block_writeback_##wb() \
#define arm_block_address_preadjust_down_full(wb) \
mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], \
-((word_bit_count(reg_list)) * 4)); \
arm_block_writeback_##wb() \
#define arm_block_address_preadjust_down(wb) \
mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], \
-(((word_bit_count(reg_list)) * 4) - 4)); \
arm_block_writeback_##wb()
#define arm_block_address_preadjust_no(wb) \
mips_emit_addu(reg_a2, arm_to_mips_reg[rn], reg_zero) \
#define arm_block_address_postadjust_no() \
#define arm_block_address_postadjust_up() \
mips_emit_addiu(arm_to_mips_reg[rn], reg_a2, \
((word_bit_count(reg_list)) * 4)) \
#define arm_block_address_postadjust_down() \
mips_emit_addiu(arm_to_mips_reg[rn], reg_a2, \
-((word_bit_count(reg_list)) * 4)) \
// ARM: rn *must* be different from rm and rd. rm *can* be the same as rd.
#define arm_swap(type) \