Rework ram block ptrs to remove second indirection table.
This removes ram_block_ptrs and encodes the pointer directly in the block tag. Saves ~256KB at no performance cost. Drawback is that it limits the ram cache size to 512KB (we were using 768KB before). Should not be a problem since most games use less than 32KB of cache anyway. Fixed ARM routines accordingly.
This commit is contained in:
David Guillen Fandos
parent
aded681de2
commit
3144d9e277
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@ -179,6 +179,7 @@ execute_pc_##mode: ;\
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.long 3f /* F Bad region */;\
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;\
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3: ;\
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/* r0 already contains the PC to jump to */ ;\
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call_c_function(block_lookup_address_##mode) ;\
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restore_flags() ;\
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bx r0 ;\
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@ -187,23 +188,23 @@ execute_pc_##mode: ;\
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mov r2, r0, lsl #14 /* addr &= 0x3ffff */;\
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mov r2, r2, lsr #14 ;\
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ldrh r2, [r1, r2] /* Load half word there */;\
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ldr r1, =(ram_block_ptrs) ;\
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ldr r1, [r1, r2, lsl #2] /* Pointer to the cache */;\
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cmp r1, #0 /* NULL means not translated */;\
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beq 3b /* Need to translate */;\
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ldr r1, =(ram_translation_cache) ;\
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subs r2, #0x0104 /* Check valid tag + rebase */;\
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ble 3b /* Data/non-entry code -> transl.*/;\
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mov r2, r2, lsr #1 /* Ignores LSB */;\
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restore_flags() ;\
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bx r1 ;\
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add pc, r1, r2, lsl #4 /* Offset is 16 byte aligned */;\
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2: ;\
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ldr r1, =(iwram) /* Load base addr */;\
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mov r2, r0, lsl #17 /* addr &= 0x7fff */;\
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mov r2, r2, lsr #17 ;\
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ldrh r2, [r1, r2] /* Load half word there */;\
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ldr r1, =(ram_block_ptrs) ;\
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ldr r1, [r1, r2, lsl #2] /* Pointer to the cache */;\
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cmp r1, #0 /* NULL means not translated */;\
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beq 3b /* Need to translate */;\
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ldr r1, =(ram_translation_cache) ;\
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subs r2, #0x0104 /* Check valid tag + rebase */;\
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ble 3b /* Data/non-entry code -> transl.*/;\
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mov r2, r2, lsr #1 /* Ignores LSB */;\
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restore_flags() ;\
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bx r1 ;\
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add pc, r1, r2, lsl #4 /* Offset is 16 byte aligned */;\
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.size arm_indirect_branch_##mode, .-arm_indirect_branch_##mode
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execute_pc_builder(arm, 0x3)
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@ -2440,8 +2440,27 @@ void translate_icache_sync() {
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block_data[block_data_position].flag_data = flag_status; \
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} \
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u8 *ram_block_ptrs[1024 * 64];
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u32 ram_block_tag_top = 0x0101;
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// I/EWRAM memory tagging
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// Code emitted in the RAM cache has tags (16 bit values) in the mirror tag ram
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// that indicate that the address contains code. The following values are used:
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// 0x0000 : this is just data (never translated)
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// 0x00XX : not used (since first byte is zero)
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// 0x0101 : this is code that is not the start of a translated block
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// 0x0105 : first possible tag (we do not use 103 due to arm asm immediates)
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// 0xXXXX : this is the start of a translated block
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//
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// The tag value is a pointer to the ram cache where the translated block starts
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// The tag value must have both bytes set to non-zero, therefore the LSB is
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// always 1 and starts from 0x0101 value.
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// The 15 value is an index to 16 byte blocks in the RAM CACHE, therefore this
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// cache is limited to ~ 2^15 * 16byte ~= 512KB
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#define CODE_TAG_BLOCK16 0x0101
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#define CODE_TAG_BLOCK32 0x01010101
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#define INITIAL_TOP_TAG 0x0105
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#define TAG2ADDR(tag) (&ram_translation_cache[((((tag) - INITIAL_TOP_TAG) >> 1) << 4)])
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#define ADDR2TAG(addr) ((((((u8*)addr) - &ram_translation_cache[0]) >> 4) << 1) + INITIAL_TOP_TAG)
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#define VALIDTAG(tag) (tag >= INITIAL_TOP_TAG)
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// This function will return a pointer to a translated block of code. If it
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// doesn't exist it will translate it, if it does it will pass it back.
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@ -2493,41 +2512,38 @@ u32 ram_block_tag_top = 0x0101;
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mem_type##_translation_region, smc_enable); \
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} \
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// 0x0101 is the smallest tag that can be used. 0xFFFF is marked
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// in the middle of blocks and used for write guarding, it doesn't
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// indicate a valid block either (it's okay to compile a new block
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// that overlaps the earlier one, although this should be relatively
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// uncommon)
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#define fill_tag_arm(tag) \
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location[0] = (tag); \
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location[1] = CODE_TAG_BLOCK16
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#define fill_tag_arm(mem_type) \
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location[0] = mem_type##_block_tag_top; \
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location[1] = 0xFFFF \
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#define fill_tag_thumb(tag) \
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*location = (tag)
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#define fill_tag_thumb(mem_type) \
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*location = mem_type##_block_tag_top \
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#define fill_tag_dual(mem_type) \
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#define fill_tag_dual(tag) \
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if(thumb) \
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fill_tag_thumb(mem_type); \
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else \
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fill_tag_arm(mem_type) \
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fill_tag_thumb(tag); \
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else { \
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fill_tag_arm(tag); \
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} \
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#define block_lookup_translate(instruction_type, mem_type, smc_enable) \
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#define block_lookup_translate_ram(instruction_type) \
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block_tag = *location; \
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if((block_tag < 0x0101) || (block_tag == 0xFFFF)) \
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if(!VALIDTAG(block_tag)) \
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{ \
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__label__ redo; \
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s32 translation_result; \
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\
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redo: \
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\
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translation_recursion_level++; \
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block_address = mem_type##_translation_ptr + block_prologue_size; \
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mem_type##_block_ptrs[mem_type##_block_tag_top] = block_address; \
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fill_tag_##instruction_type(mem_type); \
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mem_type##_block_tag_top++; \
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/* Pad the start of the block to 16 bytes, see "memory tagging" above */ \
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while ((((uintptr_t)ram_translation_ptr) % 16) != block_prologue_size) \
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ram_translation_ptr++; \
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\
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block_lookup_translate_##instruction_type(mem_type, smc_enable); \
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translation_recursion_level++; \
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block_address = ram_translation_ptr + block_prologue_size; \
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fill_tag_##instruction_type(ADDR2TAG(block_address)); \
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\
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block_lookup_translate_##instruction_type(ram, 1); \
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translation_recursion_level--; \
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\
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/* If the translation failed then pass that failure on if we're in \
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@ -2545,7 +2561,7 @@ u32 ram_block_tag_top = 0x0101;
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} \
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else \
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{ \
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block_address = mem_type##_block_ptrs[block_tag]; \
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block_address = (u8*)TAG2ADDR(block_tag); \
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} \
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u32 translation_recursion_level = 0;
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@ -2569,12 +2585,12 @@ u8 function_cc *block_lookup_address_##type(u32 pc) \
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{ \
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case 0x2: \
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location = (u16 *)(ewram + (pc & 0x3FFFF) + 0x40000); \
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block_lookup_translate(type, ram, 1); \
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block_lookup_translate_ram(type); \
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break; \
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\
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case 0x3: \
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location = (u16 *)(iwram + (pc & 0x7FFF)); \
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block_lookup_translate(type, ram, 1); \
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block_lookup_translate_ram(type); \
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break; \
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\
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case 0x0: \
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@ -2879,7 +2895,7 @@ block_exit_type block_exits[MAX_EXITS];
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if(address32(pc_address_block, (block_end_pc & 0x7FFF) + offset) == 0) \
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{ \
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address32(pc_address_block, (block_end_pc & 0x7FFF) + offset) = \
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0xFFFFFFFF; \
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CODE_TAG_BLOCK32; \
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} \
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}
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@ -2887,7 +2903,8 @@ block_exit_type block_exits[MAX_EXITS];
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int offset = (pc < 0x03000000) ? 0x40000 : -0x8000; \
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if(address16(pc_address_block, (block_end_pc & 0x7FFF) + offset) == 0) \
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{ \
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address16(pc_address_block, (block_end_pc & 0x7FFF) + offset) = 0xFFFF; \
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address16(pc_address_block, (block_end_pc & 0x7FFF) + offset) = \
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CODE_TAG_BLOCK16; \
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} \
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}
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@ -3405,7 +3422,6 @@ void flush_translation_cache_ram(void)
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last_ram_translation_ptr = ram_translation_cache;
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ram_translation_ptr = ram_translation_cache;
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ram_block_tag_top = 0x0101;
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// Proceed to clean the SMC area if needed
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// (also try to memset as little as possible for performance)
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@ -3446,8 +3462,6 @@ void init_caches(void)
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iwram_code_min = 0;
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iwram_code_max = 0x7FFF;
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flush_translation_cache_ram();
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/* Ensure 0 and FFFF get zeroed out */
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memset(ram_block_ptrs, 0, sizeof(ram_block_ptrs));
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}
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#define cache_dump_prefix ""
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@ -4,15 +4,18 @@
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/* Cache sizes and their config knobs */
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#if defined(PSP)
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4)
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 1024 * 2)
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#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 2)
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#else
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4 * 5)
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#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384 * 2)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 32)
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 1024 * 10)
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#define RAM_TRANSLATION_CACHE_SIZE (1024 * 512)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 8)
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#endif
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/* Please note that RAM_TRANSLATION_CACHE_SIZE is limited to 512KB
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Check cpu_threaded.c for "memory tagging" for more info. */
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/* This is MIPS specific for now */
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#define STUB_ARENA_SIZE (16*1024)
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