Commit Graph

55 Commits

Author SHA1 Message Date
David Guillen Fandos 60155e0b81 Add preliminary support for PS2 devices 2021-07-22 18:30:45 +02:00
David Guillen Fandos a8d99d993f Fix potential MIPS issue on cache alignment 2021-07-19 18:55:42 +02:00
David Guillen Fandos 3144d9e277 Rework ram block ptrs to remove second indirection table.
This removes ram_block_ptrs and encodes the pointer directly in the
block tag. Saves ~256KB at no performance cost.
Drawback is that it limits the ram cache size to 512KB (we were using
768KB before). Should not be a problem since most games use less than
32KB of cache anyway.

Fixed ARM routines accordingly.
2021-07-08 21:29:48 +02:00
David Guillen Fandos 0ca87a4807 Fix conditional ARM instructions at the end of a translation block
This fixes issue #133

The explanation is as follows. Most blocks end on an inconditional
jump/branch, but there's two cases where this doesn't happen:
translation gates and when we hit MAX_EXITS. These are very uncommon
cases and therefore more prone to hidden bugs.

When this happens, the last instruction emits a conditional jump (via
arm_conditional_block_header macro) which is patched by a later
instruction via generate_branch_patch_conditional. Typically the last
unconditional branch will trigger the patching condition (which is
aproximately condition != last_condition), but in these two cases it
might not happen, leaving an unpatched branch. This makes x86 and ARM
dynarecs crash in interesting ways (although it might not crash
depending on $stuff and make the bug even harder to track).
2021-07-05 18:19:19 +02:00
David Guillen Fandos aafde6de7b Add ROM mirroring and fix mult. cycle count
This should correct some minor issues in some games.
2021-05-17 01:16:56 +02:00
David Guillen Fandos 37430f22c5 Small optimization (~2-4%) and whitespace cleanup!
Cleans up a ton of whitespace in cpu.c (like 100KB!) and improves
readability of some massive decode statements.

Added an optimization for PC-relative loads (pool load) in ROM (since
it's read only and cannot possibily change) that directly emits an
immediate load. This is way faster, specially in MIPS/x86, ARM can be
even faster if we rewrite the immediate load macros to also use a pool.
2021-05-07 20:41:54 +02:00
David Guillen Fandos 4fd456e158 Adding Code Breaker cheat support
This works on both interpreter and dynarec.
Tested in MIPS, ARM and x86, still needs some more testing, some edge
cases can be buggy.
2021-05-05 21:15:27 +02:00
David Guillen Fandos 5b5a4db6c2 Add instruction tracing, for testing purposes 2021-04-03 00:37:42 +02:00
David Guillen Fandos 71ebc49b59 Improve indirect jumps in ARM
Handle already translated blocks in the ARM asm to speed up indirect
branches (affect some games more than others)
2021-03-30 21:06:52 +02:00
David Guillen Fandos ff510e7f7a Move caches to stub files to get around gcc 10
Seems that using the __atribute__ magic for sections is not the best way
of doing this, since it injects some default atributtes that collide
with the user defined ones. Using assembly is far easier in this case.

Reworked definitions a bit to make it easier to import from assembly.
Also wrapped stuff around macros for easy and less verbose
implementation of the symbol prefix issue.
2021-03-23 20:02:44 +01:00
David Guillen Fandos 11ec213c99 Make ewram memory lineal
This saves a few cycles in MIPS and simplifies a bit the core.
Removed the write map, only affects interpreter performance very
minimally. Rewired ARM and x86 handlers to support direct access to
I/EWRAM (and VRAM on ARM) to compensate. Overall performance is slightly
better but code is cleaner and allows for further improvements in the
dynarecs.
2021-03-23 19:09:56 +01:00
David Guillen Fandos eab44b9e0b Enable runtime dynarec enable/disable
Added a more thorough cache cleanup for reset/mode-change too.
Fixed the mmap initialization that ends up leaking memory.
Minor x86 asm fixes for Android.
2021-03-17 21:05:49 +01:00
David Guillen Fandos fb7ca09b01 Remove BIOS reserved translation area
This is not really necessary since it can share area with ROM.
Performance impact should be very minimal (haven't noticed it myself)
and could be compensated (even by a positive offset) if we bump the ROM
cache area size.
Tested with several dynarecs.
2021-03-17 18:33:02 +01:00
David Guillen Fandos 5ffd2832e8 Rewrite of the MIPS dynarec stubs
This allows us to emit the handlers directly in a more efficient manner.
At the same time it allows for an easy fix to emit PIC code, which is
necessary for libretro. This also enables more platform specific
optimizations and variations, perhaps even run-time multiplatform
support.
2021-03-16 22:58:58 +01:00
David Guillen Fandos 1e8097ac79 Improve and simplify dynarec JIT area.
Also fix a regression on VITA.
Use gcc/OS cache flushing routines for MIPS32 instead of synci
2021-03-12 18:05:48 +01:00
David Guillen Fandos 462f0e9784 Improve cache flush magic
Make it better and more generic. Add support for MIPS32 and fix the
messy PSP code.
2021-03-12 01:46:09 +01:00
David Guillen Fandos 5127f4b5cc Remove PSP-specific stuff from MIPS backend
This is unnecessary since newlib supports all file I/O.
This is needed for other mips ports
2021-03-10 18:41:37 +01:00
David Guillen Fandos 0522d9a4f5 Add workaround for Android ARM builds
While we are at it, use ARM mode for better performance.
2021-03-09 19:29:18 +01:00
David Guillen Fandos 3d558413fd Fix x86 dynarec, broken by d10c4afe
The dynarec expects function args to be located in registers instead of
the stack, which is not the default calling convetion in GCC/clang.
2021-03-06 21:15:22 +01:00
David Guillen Fandos 89bd699837 Reduce executable size by 90%
Turns out most of that file ends up in JIT section, which is RWX and not
a very nice way to run code really (security issues aside).
This also makes possible to build that file with -ggdb otherwise it
complains about stuff.
2021-03-05 01:14:31 +01:00
David Guillen Fandos ed3ba2c18b More cleanups (mostly whitespace and unused stuff) 2021-02-15 21:51:49 +01:00
David Guillen Fandos 7aaa280b9f Fix ARM dynarec
Turns out there were a couple of very interesting and hard to track
bugs. A missing comma made the reg list too short, leaving the 31th
element at the mercy of the linker ordering algorithm, which seems to
work in some cases depending on the compiler version.
Also the cache flush code seemed not to work on my machine (OGA),
not sure why it wored in the past :/
2021-02-10 02:46:45 +01:00
Francisco José García García 5afe4c2a39 [VITA] Fixes bug causing dynarec stuttering 2019-11-09 13:54:30 +01:00
bmaupin a60de42f3a Get dynarec working again for PSP 2019-10-20 14:58:51 -04:00
Francisco José García García a20e1c9d3a Remove RW_INIT 2016-10-04 14:20:51 +02:00
Francisco José García García adcf1c6f73 (VITA) Dynarec changes 2016-10-04 07:32:54 +00:00
Francisco José García García 6bfb7e1b47 (VITA) Dynarec working 2016-10-03 20:19:11 +02:00
twinaphex 7313c9cd61 Fix build issues 2016-08-15 03:48:39 +02:00
Francisco José García García 44b63e7d28 (VITA) Dynarec WIP 2016-08-14 18:28:25 +02:00
Francisco José García García 6ab0992ecf (VITA) Dynarec WIP 2016-08-08 00:31:21 +02:00
aliaspider f1d14fbe7c (3ds) dynarec: map the translation caches to specific addresses at
runtime, increases compatibility with loaders that can reloacate each
program section seperately.
move the svc enabling functions to the frontend.
2015-11-04 15:46:27 +01:00
aliaspider c1d061e204 (3DS) add dynarec support when started from a .cia install
use libkhax for ninjhax 1.0
2015-09-11 22:02:04 +01:00
aliaspider 5b6683bb93 (3DS) enable dynarec support, works only with ninjahax. 2015-04-08 10:20:32 +01:00
Twinaphex d10c4afea2 Get rid of function_cc 2014-12-20 09:14:38 +01:00
twinaphex cefd5b63ee Remove a lot of the GNU case range extensions instances 2014-12-13 04:50:48 +01:00
twinaphex 5b59ef3acc Reimplement cache invalidation code 2014-12-11 18:47:48 +01:00
twinaphex c78a0dd39b (Android) For Android x86 build - try to use mmap, for Android - use ARM_MEMORY_DYNAREC
codepath
2014-12-11 01:38:47 +01:00
twinaphex eeeff89a2c (Android) Works now with dynarec 2014-12-10 21:12:45 +01:00
twinaphex e33a56cd83 PC_BUILD can go now 2014-12-10 18:53:06 +01:00
twinaphex 82731290ee We don't need to get rid of idle loop patching for non-dynarec
core
2014-12-10 17:27:18 +01:00
twinaphex 51d78afa09 Add HAVE_DYNAREC ifdef 2014-12-10 17:06:09 +01:00
twinaphex 512f7f5b27 Code nits - get rid of '== NULL' / '!= NULL' 2014-12-10 16:40:43 +01:00
twinaphex 7a0b0cba45 Style nits 2014-12-10 15:47:19 +01:00
aliaspider a926a68eb3 cleanups 2014-12-10 12:53:26 +01:00
aliaspider 6d7fd87e07 add a HAVE_MMAP check, cleanups. 2014-12-10 12:29:19 +01:00
twinaphex 1a8b77c185 Demacro-ize block_builder_arm/block_builder_thumb 2014-12-10 01:25:37 +01:00
twinaphex fe19474dca Add macro parameter 'opcode' to some macros 2014-12-10 01:17:37 +01:00
aliaspider 1a6a136801 dynamic recompiler now works when the core is compiled as a shared
library.
2014-12-09 09:54:33 +01:00
notaz bbba320911 enable -Wall and fix warnings reported by it 2011-09-06 00:18:06 +03:00
notaz 8b6232a675 fix some warnings 2011-09-03 01:31:26 +03:00