Improve and simplify dynarec JIT area.
Also fix a regression on VITA. Use gcc/OS cache flushing routines for MIPS32 instead of synci
This commit is contained in:
David Guillen Fandos
parent
462f0e9784
commit
1e8097ac79
15
Makefile
15
Makefile
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@ -166,12 +166,12 @@ else ifeq ($(platform), qnx)
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fpic := -fPIC
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SHARED := -shared -Wl,--version-script=link.T
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HAVE_MMAP = 1
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CPU_ARCH := arm
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CC = qcc -Vgcc_ntoarmv7le
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AR = qcc -Vgcc_ntoarmv7le
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CFLAGS += -D__BLACKBERRY_QNX_
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HAVE_DYNAREC := 1
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CFLAGS += -DARM -DARM_ARCH -DARM_MEMORY_DYNAREC
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# Lightweight PS3 Homebrew SDK
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else ifeq ($(platform), psl1ght)
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@ -238,10 +238,8 @@ else ifeq ($(platform), rpi3)
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TARGET := $(TARGET_NAME)_libretro.so
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fpic := -fPIC
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SHARED := -shared -Wl,--version-script=link.T -Wl,--no-undefined
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CFLAGS += -DARM -DARM_ARCH
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CFLAGS += -marm -mcpu=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=hard
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CFLAGS += -fomit-frame-pointer -ffast-math
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CFLAGS += -DARM_MEMORY_DYNAREC
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CXXFLAGS = $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
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CPU_ARCH := arm
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HAVE_DYNAREC = 1
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@ -251,10 +249,8 @@ else ifeq ($(platform), rpi2)
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TARGET := $(TARGET_NAME)_libretro.so
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fpic := -fPIC
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SHARED := -shared -Wl,--version-script=link.T -Wl,--no-undefined
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CFLAGS += -DARM -DARM_ARCH
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CFLAGS += -marm -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard
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CFLAGS += -fomit-frame-pointer -ffast-math
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CFLAGS += -DARM_MEMORY_DYNAREC
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CXXFLAGS = $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
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CPU_ARCH := arm
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HAVE_DYNAREC = 1
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@ -264,10 +260,9 @@ else ifeq ($(platform), rpi1)
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TARGET := $(TARGET_NAME)_libretro.so
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fpic := -fPIC
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SHARED := -shared -Wl,--version-script=link.T -Wl,--no-undefined
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CFLAGS += -DARM11 -DARM_ARCH
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CFLAGS += -DARM11
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CFLAGS += -marm -mfpu=vfp -mfloat-abi=hard -march=armv6j
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CFLAGS += -fomit-frame-pointer -ffast-math
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CFLAGS += -DARM_MEMORY_DYNAREC
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CXXFLAGS = $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
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CPU_ARCH := arm
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HAVE_DYNAREC = 1
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@ -298,8 +293,6 @@ else ifeq ($(platform), classic_armv7_a7)
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BUILTIN_GPU = neon
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CPU_ARCH := arm
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HAVE_DYNAREC = 1
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CFLAGS += -DARM -DARM_ARCH
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CFLAGS += -DARM_MEMORY_DYNAREC
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ifeq ($(shell echo `$(CC) -dumpversion` "< 4.9" | bc -l), 1)
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CFLAGS += -march=armv7-a
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else
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@ -363,11 +356,9 @@ else ifneq (,$(findstring armv,$(platform)))
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CFLAGS += -mfloat-abi=hard
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ASFLAGS += -mfloat-abi=hard
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endif
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CFLAGS += -DARM -DARM_ARCH
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# Dynarec works at least in rpi, take a look at issue #11
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ifeq (,$(findstring no-dynarec,$(platform)))
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HAVE_DYNAREC := 1
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CFLAGS += -DARM_MEMORY_DYNAREC
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endif
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LDFLAGS := -Wl,--no-undefined
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@ -429,6 +420,8 @@ endif
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ifeq ($(CPU_ARCH), arm)
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DEFINES += -DARM_ARCH
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else ifeq ($(CPU_ARCH), mips)
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DEFINES += -DMIPS_ARCH
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else ifeq ($(CPU_ARCH), x86_32)
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DEFINES += -DX86_ARCH
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endif
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@ -53,7 +53,7 @@ u8* bios_translation_cache_ptr;
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u8 *rom_translation_ptr = rom_translation_cache;
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u8 *ram_translation_ptr = ram_translation_cache;
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u8 *bios_translation_ptr = bios_translation_cache;
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#elif defined(ARM_MEMORY_DYNAREC)
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#else
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#ifdef __ANDROID__
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// Workaround for 'attempt to map x bytes at offset y'
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@ -75,13 +75,6 @@ u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE]
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u8 *bios_translation_ptr = bios_translation_cache;
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__asm__(".section .text");
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#else
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u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE];
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u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE];
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u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE];
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u8 *rom_translation_ptr = rom_translation_cache;
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u8 *ram_translation_ptr = ram_translation_cache;
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u8 *bios_translation_ptr = bios_translation_cache;
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#endif
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u32 iwram_code_min = 0xFFFFFFFF;
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@ -234,19 +227,13 @@ extern u8 bit_count[256];
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#define thumb_decode_branch() \
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u32 offset = opcode & 0x07FF \
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#ifdef PSP
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#include "psp/mips_emit.h"
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/* Include the right emitter headers */
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#if defined(MIPS_ARCH)
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#include "psp/mips_emit.h"
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#elif defined(ARM_ARCH)
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#include "arm/arm_emit.h"
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#include "arm/arm_emit.h"
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#else
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#include "x86/x86_emit.h"
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#include "x86/x86_emit.h"
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#endif
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/* Cache invalidation */
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@ -258,7 +245,7 @@ extern u8 bit_count[256];
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}
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#elif defined(VITA)
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void platform_cache_sync(void *baseaddr, void *endptr) {
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sceKernelSyncVMDomain(baseaddr, ((char*)endptr) - ((char*)baseaddr) + 64);
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sceKernelSyncVMDomain(sceBlock, baseaddr, ((char*)endptr) - ((char*)baseaddr) + 64);
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}
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#elif defined(_3DS)
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#include "3ds/3ds_utils.h"
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@ -271,7 +258,7 @@ extern u8 bit_count[256];
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}
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#elif defined(MIPS_ARCH)
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void platform_cache_sync(void *baseaddr, void *endptr) {
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icache_region_sync(baseaddr, ((char*)endptr) - ((char*)baseaddr));
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__builtin___clear_cache(baseaddr, endptr);
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}
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#else
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/* x86 CPUs have icache consistency checks */
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@ -9,7 +9,7 @@ HAVE_DYNAREC :=
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COREFLAGS := -DINLINE=inline -D__LIBRETRO__ -DFRONTEND_SUPPORTS_RGB565
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ifeq ($(TARGET_ARCH),arm)
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COREFLAGS += -DARM_ARCH -DARM_MEMORY_DYNAREC
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COREFLAGS += -DARM_ARCH
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CPU_ARCH := arm
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HAVE_DYNAREC := 1
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else ifeq ($(TARGET_ARCH),x86)
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@ -2808,24 +2808,8 @@ execute_arm_translate:
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jr $2 # jump to return
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nop
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# This is only to be used with MIPS32
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# $4: start location
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# $5: length
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icache_region_sync:
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ins $4, $0, 0, 6 # align to 64 bytes
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addiu $2, $5, 63 # align up to 64 bytes
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srl $2, $2, 6 # divide by 64
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1:
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synci ($4) # sync caches
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addiu $2, $2, -1 # next loop iteration
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bne $2, $0, 1b # loop
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addiu $4, $4, 64 # go to next cache line (delay slot)
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jr $ra # return
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nop
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.data:
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memory_map_read:
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.space 0x8000
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