Fix potential MIPS issue on cache alignment

2021-07-19 18:55:42 +02:00 · 2021-07-19 18:55:42 +02:00 · a8d99d993f
parent 3eddcf8416
commit a8d99d993f
1 changed files with 2 additions and 1 deletions
--- a/cpu_threaded.c
+++ b/cpu_threaded.c
@ -2536,7 +2536,8 @@ void translate_icache_sync() {
    redo:                                                                     \
                                                                              \
    /* Pad the start of the block to 16 bytes, see "memory tagging" above */  \
-    while ((((uintptr_t)ram_translation_ptr) % 16) != block_prologue_size)    \
+    while (((uintptr_t)(&ram_translation_ptr[block_prologue_size]             \
+                                          - ram_translation_cache)) % 16)     \
      ram_translation_ptr++;                                                  \
                                                                              \
    translation_recursion_level++;                                            \