From a8d99d993fc510c66bd2e8a16d0fcd5efafb2672 Mon Sep 17 00:00:00 2001 From: David Guillen Fandos Date: Mon, 19 Jul 2021 18:55:42 +0200 Subject: [PATCH] Fix potential MIPS issue on cache alignment --- cpu_threaded.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cpu_threaded.c b/cpu_threaded.c index d1a338c..1346528 100644 --- a/cpu_threaded.c +++ b/cpu_threaded.c @@ -2536,7 +2536,8 @@ void translate_icache_sync() { redo: \ \ /* Pad the start of the block to 16 bytes, see "memory tagging" above */ \ - while ((((uintptr_t)ram_translation_ptr) % 16) != block_prologue_size) \ + while (((uintptr_t)(&ram_translation_ptr[block_prologue_size] \ + - ram_translation_cache)) % 16) \ ram_translation_ptr++; \ \ translation_recursion_level++; \