Fix x86 dynarec, broken by d10c4afe
The dynarec expects function args to be located in registers instead of the stack, which is not the default calling convetion in GCC/clang.
This commit is contained in:
David Guillen Fandos
parent
d21478e06e
commit
3d558413fd
2
Makefile
2
Makefile
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@ -442,6 +442,8 @@ endif
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ifeq ($(CPU_ARCH), arm)
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DEFINES += -DARM_ARCH
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else ifeq ($(CPU_ARCH), x86_32)
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DEFINES += -DX86_ARCH
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endif
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6
common.h
6
common.h
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@ -31,6 +31,12 @@
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#define PATH_SEPARATOR_CHAR '/'
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#endif
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#ifdef X86_ARCH
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#define function_cc __attribute__((regparm(2)))
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#else
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#define function_cc
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#endif
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#ifdef ARM_ARCH
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#define _BSD_SOURCE // sync
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23
cpu.h
23
cpu.h
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@ -99,21 +99,22 @@ void execute_arm(u32 cycles);
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void raise_interrupt(irq_type irq_raised);
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void set_cpu_mode(cpu_mode_type new_mode);
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u32 execute_load_u8(u32 address);
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u32 execute_load_u16(u32 address);
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u32 execute_load_u32(u32 address);
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u32 execute_load_s8(u32 address);
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u32 execute_load_s16(u32 address);
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void execute_store_u8(u32 address, u32 source);
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void execute_store_u16(u32 address, u32 source);
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void execute_store_u32(u32 address, u32 source);
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u32 execute_arm_translate(u32 cycles);
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u32 function_cc execute_load_u8(u32 address);
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u32 function_cc execute_load_u16(u32 address);
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u32 function_cc execute_load_u32(u32 address);
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u32 function_cc execute_load_s8(u32 address);
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u32 function_cc execute_load_s16(u32 address);
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void function_cc execute_store_u8(u32 address, u32 source);
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void function_cc execute_store_u16(u32 address, u32 source);
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void function_cc execute_store_u32(u32 address, u32 source);
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u32 function_cc execute_arm_translate(u32 cycles);
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void init_translater(void);
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void cpu_write_savestate(void);
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void cpu_read_savestate(void);
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u8 *block_lookup_address_arm(u32 pc);
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u8 *block_lookup_address_thumb(u32 pc);
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u8 function_cc *block_lookup_address_arm(u32 pc);
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u8 function_cc *block_lookup_address_thumb(u32 pc);
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u8 function_cc *block_lookup_address_dual(u32 pc);
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s32 translate_block_arm(u32 pc, translation_region_type translation_region,
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u32 smc_enable);
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s32 translate_block_thumb(u32 pc, translation_region_type translation_region,
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@ -2839,7 +2839,7 @@ u32 translation_flush_count = 0;
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#define block_lookup_address_builder(type) \
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u8 *block_lookup_address_##type(u32 pc) \
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u8 function_cc *block_lookup_address_##type(u32 pc) \
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{ \
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u16 *location; \
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u32 block_tag; \
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@ -2848,8 +2848,7 @@ u8 *block_lookup_address_##type(u32 pc) \
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/* Starting at the beginning, we allow for one translation cache flush. */ \
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if(translation_recursion_level == 0){ \
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translation_flush_count = 0; \
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\
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} \
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} \
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block_lookup_address_pc_##type(); \
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\
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switch(pc >> 24) \
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28
gba_memory.c
28
gba_memory.c
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@ -437,7 +437,7 @@ u32 eeprom_address = 0;
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s32 eeprom_counter = 0;
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u8 eeprom_buffer[8];
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void write_eeprom(u32 address, u32 value)
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void function_cc write_eeprom(u32 address, u32 value)
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{
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switch(eeprom_mode)
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{
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@ -554,7 +554,7 @@ void write_eeprom(u32 address, u32 value)
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value = current_instruction | (current_instruction << 16); \
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} \
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u32 read_eeprom(void)
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u32 function_cc read_eeprom(void)
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{
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u32 value;
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@ -757,7 +757,7 @@ static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
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#define access_register16_low(address) \
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value = ((address16(io_registers, address + 2)) << 16) | value \
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cpu_alert_type write_io_register8(u32 address, u32 value)
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cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
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{
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switch(address)
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{
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@ -1173,7 +1173,7 @@ cpu_alert_type write_io_register8(u32 address, u32 value)
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return CPU_ALERT_NONE;
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}
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cpu_alert_type write_io_register16(u32 address, u32 value)
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cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
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{
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switch(address)
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{
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@ -1426,7 +1426,7 @@ cpu_alert_type write_io_register16(u32 address, u32 value)
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}
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cpu_alert_type write_io_register32(u32 address, u32 value)
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cpu_alert_type function_cc write_io_register32(u32 address, u32 value)
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{
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switch(address)
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{
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@ -1505,7 +1505,7 @@ cpu_alert_type write_io_register32(u32 address, u32 value)
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} \
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void write_backup(u32 address, u32 value)
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void function_cc write_backup(u32 address, u32 value)
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{
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value &= 0xFF;
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@ -1703,7 +1703,7 @@ static u32 encode_bcd(u8 value)
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\
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address16(map, update_address & 0x7FFF) = _value \
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void write_rtc(u32 address, u32 value)
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void function_cc write_rtc(u32 address, u32 value)
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{
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u32 rtc_page_index;
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u32 update_address;
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@ -1970,14 +1970,14 @@ void write_rtc(u32 address, u32 value)
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break; \
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} \
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u8 read_memory8(u32 address)
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u8 function_cc read_memory8(u32 address)
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{
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u8 value;
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read_memory(8);
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return value;
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}
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u16 read_memory16_signed(u32 address)
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u16 function_cc read_memory16_signed(u32 address)
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{
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u16 value;
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@ -1991,7 +1991,7 @@ u16 read_memory16_signed(u32 address)
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// unaligned reads are actually 32bit
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u32 read_memory16(u32 address)
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u32 function_cc read_memory16(u32 address)
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{
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u32 value;
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@ -2010,7 +2010,7 @@ u32 read_memory16(u32 address)
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}
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u32 read_memory32(u32 address)
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u32 function_cc read_memory32(u32 address)
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{
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u32 value;
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if(address & 0x03)
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@ -2028,19 +2028,19 @@ u32 read_memory32(u32 address)
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return value;
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}
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cpu_alert_type write_memory8(u32 address, u8 value)
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cpu_alert_type function_cc write_memory8(u32 address, u8 value)
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{
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write_memory(8);
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return CPU_ALERT_NONE;
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}
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cpu_alert_type write_memory16(u32 address, u16 value)
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cpu_alert_type function_cc write_memory16(u32 address, u16 value)
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{
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write_memory(16);
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return CPU_ALERT_NONE;
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}
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cpu_alert_type write_memory32(u32 address, u32 value)
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cpu_alert_type function_cc write_memory32(u32 address, u32 value)
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{
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write_memory(32);
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return CPU_ALERT_NONE;
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14
gba_memory.h
14
gba_memory.h
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@ -156,13 +156,13 @@ typedef enum
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FLASH_MANUFACTURER_SST = 0xBF
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} flash_manufacturer_id_type;
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u8 read_memory8(u32 address);
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u32 read_memory16(u32 address);
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u16 read_memory16_signed(u32 address);
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u32 read_memory32(u32 address);
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cpu_alert_type write_memory8(u32 address, u8 value);
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cpu_alert_type write_memory16(u32 address, u16 value);
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cpu_alert_type write_memory32(u32 address, u32 value);
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u8 function_cc read_memory8(u32 address);
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u32 function_cc read_memory16(u32 address);
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u16 function_cc read_memory16_signed(u32 address);
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u32 function_cc read_memory32(u32 address);
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cpu_alert_type function_cc write_memory8(u32 address, u8 value);
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cpu_alert_type function_cc write_memory16(u32 address, u16 value);
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cpu_alert_type function_cc write_memory32(u32 address, u32 value);
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extern u8 *memory_regions[16];
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extern u32 memory_limits[16];
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104
x86/x86_emit.h
104
x86/x86_emit.h
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@ -28,7 +28,7 @@ void x86_indirect_branch_arm(u32 address);
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void x86_indirect_branch_thumb(u32 address);
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void x86_indirect_branch_dual(u32 address);
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void execute_store_cpsr(u32 new_cpsr, u32 store_mask);
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void function_cc execute_store_cpsr(u32 new_cpsr, u32 store_mask);
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typedef enum
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{
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@ -523,7 +523,7 @@ typedef enum
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generate_function_call(execute_##name##_##flags_op##_reg); \
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generate_mov(ireg, rv) \
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u32 execute_lsl_no_flags_reg(u32 value, u32 shift)
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u32 function_cc execute_lsl_no_flags_reg(u32 value, u32 shift)
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{
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if(shift != 0)
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{
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@ -535,7 +535,7 @@ u32 execute_lsl_no_flags_reg(u32 value, u32 shift)
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return value;
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}
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u32 execute_lsr_no_flags_reg(u32 value, u32 shift)
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u32 function_cc execute_lsr_no_flags_reg(u32 value, u32 shift)
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{
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if(shift != 0)
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{
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@ -547,7 +547,7 @@ u32 execute_lsr_no_flags_reg(u32 value, u32 shift)
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return value;
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}
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u32 execute_asr_no_flags_reg(u32 value, u32 shift)
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u32 function_cc execute_asr_no_flags_reg(u32 value, u32 shift)
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{
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if(shift != 0)
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{
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@ -559,7 +559,7 @@ u32 execute_asr_no_flags_reg(u32 value, u32 shift)
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return value;
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}
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u32 execute_ror_no_flags_reg(u32 value, u32 shift)
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u32 function_cc execute_ror_no_flags_reg(u32 value, u32 shift)
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{
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if(shift != 0)
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{
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@ -570,7 +570,7 @@ u32 execute_ror_no_flags_reg(u32 value, u32 shift)
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}
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u32 execute_lsl_flags_reg(u32 value, u32 shift)
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u32 function_cc execute_lsl_flags_reg(u32 value, u32 shift)
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{
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if(shift != 0)
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{
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@ -592,7 +592,7 @@ u32 execute_lsl_flags_reg(u32 value, u32 shift)
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return value;
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}
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u32 execute_lsr_flags_reg(u32 value, u32 shift)
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u32 function_cc execute_lsr_flags_reg(u32 value, u32 shift)
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{
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if(shift != 0)
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{
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@ -614,7 +614,7 @@ u32 execute_lsr_flags_reg(u32 value, u32 shift)
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return value;
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}
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u32 execute_asr_flags_reg(u32 value, u32 shift)
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u32 function_cc execute_asr_flags_reg(u32 value, u32 shift)
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{
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if(shift != 0)
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{
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@ -632,7 +632,7 @@ u32 execute_asr_flags_reg(u32 value, u32 shift)
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return value;
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}
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u32 execute_ror_flags_reg(u32 value, u32 shift)
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u32 function_cc execute_ror_flags_reg(u32 value, u32 shift)
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{
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if(shift != 0)
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{
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@ -643,14 +643,14 @@ u32 execute_ror_flags_reg(u32 value, u32 shift)
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return value;
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}
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u32 execute_rrx_flags(u32 value)
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u32 function_cc execute_rrx_flags(u32 value)
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{
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u32 c_flag = reg[REG_C_FLAG];
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reg[REG_C_FLAG] = value & 0x01;
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return (value >> 1) | (c_flag << 31);
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}
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u32 execute_rrx(u32 value)
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u32 function_cc execute_rrx(u32 value)
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{
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return (value >> 1) | (reg[REG_C_FLAG] << 31);
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}
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@ -917,7 +917,7 @@ u32 execute_rrx(u32 value)
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generate_indirect_branch_arm(); \
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} \
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u32 execute_spsr_restore(u32 address)
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u32 function_cc execute_spsr_restore(u32 address)
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{
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if(reg[CPU_MODE] != MODE_USER)
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{
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@ -1195,7 +1195,7 @@ typedef enum
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generate_store_reg_pc_no_flags(a0, rd); \
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} \
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static void execute_mul_flags(u32 dest)
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static void function_cc execute_mul_flags(u32 dest)
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{
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calculate_z_flag(dest);
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calculate_n_flag(dest);
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@ -1223,7 +1223,7 @@ static void execute_mul_flags(u32 dest)
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arm_multiply_flags_##flags(); \
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} \
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static void execute_mul_long_flags(u32 dest_lo, u32 dest_hi)
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static void function_cc execute_mul_long_flags(u32 dest_lo, u32 dest_hi)
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{
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reg[REG_Z_FLAG] = (dest_lo == 0) & (dest_hi == 0);
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calculate_n_flag(dest_hi);
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@ -1253,13 +1253,13 @@ static void execute_mul_long_flags(u32 dest_lo, u32 dest_hi)
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arm_multiply_long_flags_##flags(); \
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} \
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u32 execute_read_cpsr(void)
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u32 function_cc execute_read_cpsr(void)
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{
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collapse_flags();
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return reg[REG_CPSR];
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}
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u32 execute_read_spsr(void)
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u32 function_cc execute_read_spsr(void)
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{
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collapse_flags();
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return spsr[reg[CPU_MODE]];
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@ -1272,7 +1272,7 @@ u32 execute_read_spsr(void)
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// store_mask and address are stored in the SAVE slots, since there's no real
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// register space to nicely pass them.
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u32 execute_store_cpsr_body(u32 _cpsr)
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u32 function_cc execute_store_cpsr_body(u32 _cpsr)
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{
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reg[REG_CPSR] = _cpsr;
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if(reg[REG_SAVE] & 0xFF)
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@ -1293,7 +1293,7 @@ u32 execute_store_cpsr_body(u32 _cpsr)
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}
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void execute_store_spsr(u32 new_spsr, u32 store_mask)
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void function_cc execute_store_spsr(u32 new_spsr, u32 store_mask)
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{
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u32 _spsr = spsr[reg[CPU_MODE]];
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spsr[reg[CPU_MODE]] = (new_spsr & store_mask) | (_spsr & (~store_mask));
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@ -1365,7 +1365,7 @@ void execute_store_spsr(u32 new_spsr, u32 store_mask)
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} \
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#define access_memory_generate_read_function(mem_size, mem_type) \
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u32 execute_load_##mem_type(u32 address) \
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u32 function_cc execute_load_##mem_type(u32 address) \
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{ \
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u32 dest; \
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read_memory(mem_size, mem_type, address, dest); \
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@ -1377,29 +1377,13 @@ access_memory_generate_read_function(8, s8);
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access_memory_generate_read_function(16, u16);
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access_memory_generate_read_function(32, u32);
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u32 execute_load_s16(u32 address)
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u32 function_cc execute_load_s16(u32 address)
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{
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u32 dest;
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read_memory_s16(address, dest);
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return dest;
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}
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#define access_memory_generate_write_function(mem_size, mem_type) \
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void execute_store_##mem_type(u32 address, u32 source) \
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{ \
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u8 *map; \
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\
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if(((address & aligned_address_mask##mem_size) == 0) && \
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(map = memory_map_write[address >> 15])) \
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{ \
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*((mem_type *)((u8 *)map + (address & 0x7FFF))) = source; \
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} \
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else \
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{ \
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write_memory##mem_size(address, source); \
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} \
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} \
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#define arm_access_memory_load(mem_type) \
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cycle_count += 2; \
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generate_function_call(execute_load_##mem_type); \
|
||||
|
|
@ -1492,7 +1476,7 @@ void execute_store_##mem_type(u32 address, u32 source) \
|
|||
#define sprint_yes(access_type, pre_op, post_op, wb) \
|
||||
printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \
|
||||
|
||||
u32 execute_aligned_load32(u32 address)
|
||||
u32 function_cc execute_aligned_load32(u32 address)
|
||||
{
|
||||
u8 *map;
|
||||
if(!(address & 0xF0000000) && (map = memory_map_read[address >> 15]))
|
||||
|
|
@ -1501,7 +1485,7 @@ u32 execute_aligned_load32(u32 address)
|
|||
return read_memory32(address);
|
||||
}
|
||||
|
||||
void execute_aligned_store32(u32 address, u32 source)
|
||||
void function_cc execute_aligned_store32(u32 address, u32 source)
|
||||
{
|
||||
u8 *map;
|
||||
|
||||
|
|
@ -1729,7 +1713,7 @@ void execute_aligned_store32(u32 address, u32 source)
|
|||
// Operation types: lsl, lsr, asr, ror
|
||||
// Affects N/Z/C flags
|
||||
|
||||
u32 execute_lsl_reg_op(u32 value, u32 shift)
|
||||
u32 function_cc execute_lsl_reg_op(u32 value, u32 shift)
|
||||
{
|
||||
if(shift != 0)
|
||||
{
|
||||
|
|
@ -1753,7 +1737,7 @@ u32 execute_lsl_reg_op(u32 value, u32 shift)
|
|||
return value;
|
||||
}
|
||||
|
||||
u32 execute_lsr_reg_op(u32 value, u32 shift)
|
||||
u32 function_cc execute_lsr_reg_op(u32 value, u32 shift)
|
||||
{
|
||||
if(shift != 0)
|
||||
{
|
||||
|
|
@ -1777,7 +1761,7 @@ u32 execute_lsr_reg_op(u32 value, u32 shift)
|
|||
return value;
|
||||
}
|
||||
|
||||
u32 execute_asr_reg_op(u32 value, u32 shift)
|
||||
u32 function_cc execute_asr_reg_op(u32 value, u32 shift)
|
||||
{
|
||||
if(shift != 0)
|
||||
{
|
||||
|
|
@ -1797,7 +1781,7 @@ u32 execute_asr_reg_op(u32 value, u32 shift)
|
|||
return value;
|
||||
}
|
||||
|
||||
u32 execute_ror_reg_op(u32 value, u32 shift)
|
||||
u32 function_cc execute_ror_reg_op(u32 value, u32 shift)
|
||||
{
|
||||
if(shift != 0)
|
||||
{
|
||||
|
|
@ -1809,7 +1793,7 @@ u32 execute_ror_reg_op(u32 value, u32 shift)
|
|||
return value;
|
||||
}
|
||||
|
||||
u32 execute_lsl_imm_op(u32 value, u32 shift)
|
||||
u32 function_cc execute_lsl_imm_op(u32 value, u32 shift)
|
||||
{
|
||||
if(shift != 0)
|
||||
{
|
||||
|
|
@ -1821,7 +1805,7 @@ u32 execute_lsl_imm_op(u32 value, u32 shift)
|
|||
return value;
|
||||
}
|
||||
|
||||
u32 execute_lsr_imm_op(u32 value, u32 shift)
|
||||
u32 function_cc execute_lsr_imm_op(u32 value, u32 shift)
|
||||
{
|
||||
if(shift != 0)
|
||||
{
|
||||
|
|
@ -1838,7 +1822,7 @@ u32 execute_lsr_imm_op(u32 value, u32 shift)
|
|||
return value;
|
||||
}
|
||||
|
||||
u32 execute_asr_imm_op(u32 value, u32 shift)
|
||||
u32 function_cc execute_asr_imm_op(u32 value, u32 shift)
|
||||
{
|
||||
if(shift != 0)
|
||||
{
|
||||
|
|
@ -1855,7 +1839,7 @@ u32 execute_asr_imm_op(u32 value, u32 shift)
|
|||
return value;
|
||||
}
|
||||
|
||||
u32 execute_ror_imm_op(u32 value, u32 shift)
|
||||
u32 function_cc execute_ror_imm_op(u32 value, u32 shift)
|
||||
{
|
||||
if(shift != 0)
|
||||
{
|
||||
|
|
@ -2057,12 +2041,12 @@ u32 execute_ror_imm_op(u32 value, u32 shift)
|
|||
const u32 _sb = src_b \
|
||||
|
||||
#define data_proc_generate_logic_function(name, expr) \
|
||||
u32 execute_##name(u32 rm, u32 rn) \
|
||||
u32 function_cc execute_##name(u32 rm, u32 rn) \
|
||||
{ \
|
||||
return expr; \
|
||||
} \
|
||||
\
|
||||
u32 execute_##name##s(u32 rm, u32 rn) \
|
||||
u32 function_cc execute_##name##s(u32 rm, u32 rn) \
|
||||
{ \
|
||||
u32 dest = expr; \
|
||||
calculate_z_flag(dest); \
|
||||
|
|
@ -2071,12 +2055,12 @@ u32 execute_##name##s(u32 rm, u32 rn) \
|
|||
} \
|
||||
|
||||
#define data_proc_generate_logic_unary_function(name, expr) \
|
||||
u32 execute_##name(u32 rm) \
|
||||
u32 function_cc execute_##name(u32 rm) \
|
||||
{ \
|
||||
return expr; \
|
||||
} \
|
||||
\
|
||||
u32 execute_##name##s(u32 rm) \
|
||||
u32 function_cc execute_##name##s(u32 rm) \
|
||||
{ \
|
||||
u32 dest = expr; \
|
||||
calculate_z_flag(dest); \
|
||||
|
|
@ -2086,12 +2070,12 @@ u32 execute_##name##s(u32 rm) \
|
|||
|
||||
|
||||
#define data_proc_generate_sub_function(name, src_a, src_b) \
|
||||
u32 execute_##name(u32 rm, u32 rn) \
|
||||
u32 function_cc execute_##name(u32 rm, u32 rn) \
|
||||
{ \
|
||||
return (src_a) - (src_b); \
|
||||
} \
|
||||
\
|
||||
u32 execute_##name##s(u32 rm, u32 rn) \
|
||||
u32 function_cc execute_##name##s(u32 rm, u32 rn) \
|
||||
{ \
|
||||
flags_vars(src_a, src_b); \
|
||||
dest = _sa - _sb; \
|
||||
|
|
@ -2100,12 +2084,12 @@ u32 execute_##name##s(u32 rm, u32 rn) \
|
|||
} \
|
||||
|
||||
#define data_proc_generate_add_function(name, src_a, src_b) \
|
||||
u32 execute_##name(u32 rm, u32 rn) \
|
||||
u32 function_cc execute_##name(u32 rm, u32 rn) \
|
||||
{ \
|
||||
return (src_a) + (src_b); \
|
||||
} \
|
||||
\
|
||||
u32 execute_##name##s(u32 rm, u32 rn) \
|
||||
u32 function_cc execute_##name##s(u32 rm, u32 rn) \
|
||||
{ \
|
||||
flags_vars(src_a, src_b); \
|
||||
dest = _sa + _sb; \
|
||||
|
|
@ -2114,7 +2098,7 @@ u32 execute_##name##s(u32 rm, u32 rn) \
|
|||
} \
|
||||
|
||||
#define data_proc_generate_sub_test_function(name, src_a, src_b) \
|
||||
void execute_##name(u32 rm, u32 rn) \
|
||||
void function_cc execute_##name(u32 rm, u32 rn) \
|
||||
{ \
|
||||
flags_vars(src_a, src_b); \
|
||||
dest = _sa - _sb; \
|
||||
|
|
@ -2122,7 +2106,7 @@ void execute_##name(u32 rm, u32 rn) \
|
|||
} \
|
||||
|
||||
#define data_proc_generate_add_test_function(name, src_a, src_b) \
|
||||
void execute_##name(u32 rm, u32 rn) \
|
||||
void function_cc execute_##name(u32 rm, u32 rn) \
|
||||
{ \
|
||||
flags_vars(src_a, src_b); \
|
||||
dest = _sa + _sb; \
|
||||
|
|
@ -2130,14 +2114,14 @@ void execute_##name(u32 rm, u32 rn) \
|
|||
} \
|
||||
|
||||
#define data_proc_generate_logic_test_function(name, expr) \
|
||||
void execute_##name(u32 rm, u32 rn) \
|
||||
void function_cc execute_##name(u32 rm, u32 rn) \
|
||||
{ \
|
||||
u32 dest = expr; \
|
||||
calculate_z_flag(dest); \
|
||||
calculate_n_flag(dest); \
|
||||
} \
|
||||
|
||||
u32 execute_neg(u32 rm) \
|
||||
u32 function_cc execute_neg(u32 rm) \
|
||||
{ \
|
||||
u32 dest = 0 - rm; \
|
||||
calculate_flags_sub(dest, 0, rm); \
|
||||
|
|
@ -2166,7 +2150,7 @@ data_proc_generate_logic_test_function(teq, rn ^ rm);
|
|||
data_proc_generate_sub_test_function(cmp, rn, rm);
|
||||
data_proc_generate_add_test_function(cmn, rn, rm);
|
||||
|
||||
static void execute_swi(u32 pc)
|
||||
static void function_cc execute_swi(u32 pc)
|
||||
{
|
||||
reg_mode[MODE_SUPERVISOR][6] = pc;
|
||||
collapse_flags();
|
||||
|
|
@ -2289,7 +2273,7 @@ u8 swi_hle_handle[256] =
|
|||
0x0 // SWI 2A: SoundGetJumpList
|
||||
};
|
||||
|
||||
void swi_hle_div(void)
|
||||
void function_cc swi_hle_div(void)
|
||||
{
|
||||
s32 result = (s32)reg[0] / (s32)reg[1];
|
||||
reg[1] = (s32)reg[0] % (s32)reg[1];
|
||||
|
|
|
|||
Loading…
Reference in New Issue