Get dynarec working again for PSP
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parent
89e55e9902
commit
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5 changed files with 34 additions and 8 deletions
2
Makefile
2
Makefile
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@ -220,6 +220,8 @@ else ifeq ($(platform), psp1)
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CFLAGS += -fomit-frame-pointer -ffast-math
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CFLAGS += -falign-functions=32 -falign-loops -falign-labels -falign-jumps
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STATIC_LINKING = 1
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HAVE_DYNAREC = 1
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CPU_ARCH := mips
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# Vita
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else ifeq ($(platform), vita)
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@ -29,6 +29,9 @@ endif
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ifeq ($(CPU_ARCH), arm)
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SOURCES_ASM += $(CORE_DIR)/arm/arm_stub.S
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endif
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ifeq ($(CPU_ARCH), mips)
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SOURCES_ASM += $(CORE_DIR)/psp/mips_stub.S
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endif
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endif
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ifeq ($(CPU_ARCH), arm)
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@ -227,7 +227,7 @@ extern u8 bit_count[256];
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u32 offset = opcode & 0x07FF \
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#ifdef PSP_BUILD
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#ifdef PSP
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#include "psp/mips_emit.h"
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@ -257,8 +257,10 @@ static INLINE void RW_END(void)
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/* Cache invalidation */
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#if defined(PSP_BUILD)
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#if defined(PSP)
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#define translate_invalidate_dcache() sceKernelDcacheWritebackAll()
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#define invalidate_icache_region(addr, size) (void)0
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#elif defined(VITA)
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#define translate_invalidate_dcache_one(which) \
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if (which##_translation_ptr > last_##which##_translation_ptr) \
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@ -1553,9 +1553,13 @@ typedef enum
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#define arm_generate_op_imm(name, load_op) \
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arm_decode_data_proc_imm(opcode); \
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ror(imm, imm, imm_ror); \
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arm_op_check_##load_op(); \
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generate_op_##name##_imm(arm_to_mips_reg[rd], arm_to_mips_reg[rn]) \
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#define arm_generate_op_imm_flags(name, load_op) \
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arm_generate_op_imm(name, load_op) \
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#define arm_data_proc(name, type, flags_op) \
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{ \
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arm_generate_op_##type(name, yes); \
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@ -2137,10 +2141,16 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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mips_emit_addiu(arm_to_mips_reg[_rd], reg_r13, (imm * 4)); \
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} \
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#define thumb_adjust_sp(value) \
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#define thumb_adjust_sp_up() \
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mips_emit_addiu(reg_r13, reg_r13, (imm * 4)); \
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#define thumb_adjust_sp_down() \
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mips_emit_addiu(reg_r13, reg_r13, -(imm * 4)); \
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#define thumb_adjust_sp(direction) \
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{ \
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thumb_decode_add_sp(); \
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mips_emit_addiu(reg_r13, reg_r13, (value)); \
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thumb_adjust_sp_##direction(); \
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} \
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// Decode types: shift, alu_op
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@ -2203,6 +2213,9 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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#define thumb_access_memory_generate_address_reg_imm(offset, reg_rb, reg_ro) \
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mips_emit_addiu(reg_a0, arm_to_mips_reg[reg_rb], (offset)) \
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#define thumb_access_memory_generate_address_reg_imm_sp(offset, reg_rb, reg_ro) \
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mips_emit_addiu(reg_a0, arm_to_mips_reg[reg_rb], (offset * 4)) \
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#define thumb_access_memory_generate_address_reg_reg(offset, reg_rb, reg_ro) \
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mips_emit_addu(reg_a0, arm_to_mips_reg[reg_rb], arm_to_mips_reg[reg_ro]) \
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@ -3343,8 +3343,13 @@ ror_zero_shift:
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execute_arm_translate:
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addu $17, $4, $0 # load cycle counter register
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lui $16, %hi(reg) # load base register
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addiu $16, %lo(reg)
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lui $4, %hi(arm_reg) # load arm_reg address into $4
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addiu $4, %lo(arm_reg)
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jal move_reg # update reg to point to arm_reg
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addu $16, $4, $0 # copy address of arm_reg into $16
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extract_flags # load flag variables
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and $1, $1, 0x20 # see if Thumb bit is set in flags
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@ -3405,9 +3410,10 @@ iac_loop:
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memory_map_read:
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.space 0x8000
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reg:
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# This must be between memory_map_read and memory_map_write because it's used
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# to calculate their addresses elsewhere in this file.
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arm_reg:
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.space 0x100
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memory_map_write:
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.space 0x8000
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