Move caches to stub files to get around gcc 10
Seems that using the __atribute__ magic for sections is not the best way of doing this, since it injects some default atributtes that collide with the user defined ones. Using assembly is far easier in this case. Reworked definitions a bit to make it easier to import from assembly. Also wrapped stuff around macros for easy and less verbose implementation of the symbol prefix issue.
This commit is contained in:
David Guillen Fandos
parent
11ec213c99
commit
ff510e7f7a
130
arm/arm_stub.S
130
arm/arm_stub.S
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@ -1,15 +1,15 @@
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#include "../gpsp_config.h"
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#define defsymbl(symbol) \
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.global symbol ; \
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.global _##symbol ; \
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symbol: \
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_##symbol:
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.text
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.align 2
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.globl invalidate_icache_region
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.globl invalidate_cache_region
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.globl memory_map_read
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.globl reg
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.globl palette_ram
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.globl palette_ram_converted
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.globl reg_mode
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.globl spsr
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#define REG_R0 (0 * 4)
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#define REG_R1 (1 * 4)
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#define REG_R2 (2 * 4)
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@ -178,10 +178,7 @@
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#define arm_update_gba_builder(name, mode, return_op) ;\
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;\
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.align 2 ;\
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.globl arm_update_gba_##name ;\
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.globl _arm_update_gba_##name ;\
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arm_update_gba_##name: ;\
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_arm_update_gba_##name: ;\
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defsymbl(arm_update_gba_##name) ;\
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load_pc_##return_op() ;\
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str r0, [reg_base, #REG_PC] /* write out the PC */;\
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;\
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@ -243,30 +240,21 @@ arm_update_gba_builder(idle_thumb, thumb, add)
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@ r0: PC to branch to
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.align 2
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.globl arm_indirect_branch_arm
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.globl _arm_indirect_branch_arm
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arm_indirect_branch_arm:
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_arm_indirect_branch_arm:
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defsymbl(arm_indirect_branch_arm)
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save_flags()
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0
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.align 2
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.globl arm_indirect_branch_thumb
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.globl _arm_indirect_branch_thumb
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arm_indirect_branch_thumb:
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_arm_indirect_branch_thumb:
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defsymbl(arm_indirect_branch_thumb)
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save_flags()
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0
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.align 2
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.globl arm_indirect_branch_dual_arm
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.globl _arm_indirect_branch_dual_arm
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arm_indirect_branch_dual_arm:
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_arm_indirect_branch_dual_arm:
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defsymbl(arm_indirect_branch_dual_arm)
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save_flags()
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tst r0, #0x01 @ check lower bit
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bne 1f @ if set going to Thumb mode
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@ -286,10 +274,7 @@ _arm_indirect_branch_dual_arm:
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bx r0 @ return
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.align 2
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.globl arm_indirect_branch_dual_thumb
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.globl _arm_indirect_branch_dual_thumb
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arm_indirect_branch_dual_thumb:
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_arm_indirect_branch_dual_thumb:
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defsymbl(arm_indirect_branch_dual_thumb)
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save_flags()
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tst r0, #0x01 @ check lower bit
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beq 1f @ if set going to ARM mode
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@ -317,10 +302,7 @@ _arm_indirect_branch_dual_thumb:
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@ r2: current PC
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.align 2
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.globl execute_store_cpsr
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.globl _execute_store_cpsr
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execute_store_cpsr:
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_execute_store_cpsr:
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defsymbl(execute_store_cpsr)
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save_flags()
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and reg_flags, r0, r1 @ reg_flags = new_cpsr & store_mask
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ldr r0, [reg_base, #REG_CPSR] @ r0 = cpsr
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@ -354,10 +336,7 @@ _execute_store_cpsr:
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@ r1: bitmask of which bits in spsr to update
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.align 2
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.globl execute_store_spsr
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.globl _execute_store_spsr
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execute_store_spsr:
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_execute_store_spsr:
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defsymbl(execute_store_spsr)
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ldr r1, =spsr @ r1 = spsr
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ldr r2, [reg_base, #CPU_MODE] @ r2 = CPU_MODE
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str r0, [r1, r2, lsl #2] @ spsr[CPU_MODE] = new_spsr
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@ -369,10 +348,7 @@ _execute_store_spsr:
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@ r0: spsr
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.align 2
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.globl execute_read_spsr
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.globl _execute_read_spsr
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execute_read_spsr:
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_execute_read_spsr:
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defsymbl(execute_read_spsr)
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ldr r0, =spsr @ r0 = spsr
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ldr r1, [reg_base, #CPU_MODE] @ r1 = CPU_MODE
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ldr r0, [r0, r1, lsl #2] @ r0 = spsr[CPU_MODE]
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@ -385,10 +361,7 @@ _execute_read_spsr:
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@ r0: current pc
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.align 2
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.globl execute_spsr_restore
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.globl _execute_spsr_restore
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execute_spsr_restore:
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_execute_spsr_restore:
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defsymbl(execute_spsr_restore)
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save_flags()
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ldr r1, =spsr @ r1 = spsr
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ldr r2, [reg_base, #CPU_MODE] @ r2 = cpu_mode
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@ -425,10 +398,7 @@ _execute_spsr_restore:
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#define execute_swi_builder(mode) ;\
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;\
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.align 2 ;\
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.globl execute_swi_##mode ;\
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.globl _execute_swi_##mode ;\
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execute_swi_##mode: ;\
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_execute_swi_##mode: ;\
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defsymbl(execute_swi_##mode) ;\
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save_flags() ;\
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ldr r1, =reg_mode /* r1 = reg_mode */;\
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/* reg_mode[MODE_SUPERVISOR][6] = pc */;\
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@ -460,10 +430,7 @@ execute_swi_builder(thumb)
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#define execute_swi_function_builder(swi_function, mode) ;\
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;\
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.align 2 ;\
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.globl execute_swi_hle_##swi_function##_##mode ;\
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.globl _execute_swi_hle_##swi_function##_##mode ;\
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execute_swi_hle_##swi_function##_##mode: ;\
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_execute_swi_hle_##swi_function##_##mode: ;\
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defsymbl(execute_swi_hle_##swi_function##_##mode) ;\
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save_flags() ;\
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store_registers_##mode() ;\
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call_c_function(execute_swi_hle_##swi_function##_c) ;\
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@ -485,10 +452,7 @@ execute_swi_function_builder(div, thumb)
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@ Uses sp as reg_base; must hold consistently true.
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.align 2
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.globl execute_arm_translate
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.globl _execute_arm_translate
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execute_arm_translate:
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_execute_arm_translate:
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defsymbl(execute_arm_translate)
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@ save the registers to be able to return later
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stmdb sp!, { r4, r5, r6, r7, r8, r9, r10, r11, r12, lr }
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@ -615,10 +579,7 @@ ext_store_ignore:
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#define execute_store_builder(store_type, store_op, load_op) ;\
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;\
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.align 2 ;\
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.globl execute_store_u##store_type ;\
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.globl _execute_store_u##store_type ;\
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execute_store_u##store_type: ;\
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_execute_store_u##store_type: ;\
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defsymbl(execute_store_u##store_type) ;\
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execute_store_body(store_type, store_op) ;\
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;\
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ext_store_u##store_type: ;\
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@ -676,10 +637,7 @@ execute_store_builder(32, str, ldr)
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@ This is a store that is executed in a strm case (so no SMC checks in-between)
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.globl execute_store_u32_safe
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.globl _execute_store_u32_safe
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execute_store_u32_safe:
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_execute_store_u32_safe:
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defsymbl(execute_store_u32_safe)
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execute_store_body(32_safe, str)
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restore_flags()
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ldr pc, [reg_base, #REG_SAVE3] @ return
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@ -822,10 +780,7 @@ lookup_pc_arm:
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#define execute_load_builder(load_type, load_function, load_op, mask) ;\
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;\
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.align 2 ;\
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.globl execute_load_##load_type ;\
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.globl _execute_load_##load_type ;\
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execute_load_##load_type: ;\
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_execute_load_##load_type: ;\
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defsymbl(execute_load_##load_type) ;\
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save_flags() ;\
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tst r0, mask /* make sure address is in range */;\
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bne ext_load_##load_type /* if not do ext load */;\
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@ -859,19 +814,38 @@ execute_load_builder(u32, 32, ldrne, #0xF0000000)
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.data
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memory_map_read:
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defsymbl(memory_map_read)
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.space 0x8000
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palette_ram:
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defsymbl(palette_ram)
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.space 0x400
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palette_ram_converted:
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defsymbl(palette_ram_converted)
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.space 0x400
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spsr:
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defsymbl(spsr)
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.space 24
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reg_mode:
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defsymbl(reg_mode)
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.space 196
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.globl reg
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.globl _reg
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reg:
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defsymbl(reg)
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.space 0x100, 0
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@ Vita and 3DS (and of course mmap) map their own cache sections through some
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@ platform-speficic mechanisms.
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#if !defined(HAVE_MMAP) && !defined(VITA) && !defined(_3DS)
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@ Make this section executable!
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.text
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#ifdef __ANDROID__
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@ Unfortunately Android builds don't like nobits, so we ship a ton of zeros
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@ TODO: Revisit this whenever we upgrade to the latest clang NDK
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.section .jit,"awx",%progbits
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#else
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.section .jit,"awx",%nobits
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#endif
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.align 4
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defsymbl(rom_translation_cache)
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.space ROM_TRANSLATION_CACHE_SIZE
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defsymbl(ram_translation_cache)
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.space RAM_TRANSLATION_CACHE_SIZE
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#endif
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19
cpu.h
19
cpu.h
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@ -20,6 +20,8 @@
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#ifndef CPU_H
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#define CPU_H
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#include "gpsp_config.h"
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// System mode and user mode are represented as the same here
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typedef enum
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@ -120,18 +122,6 @@ s32 translate_block_arm(u32 pc, translation_region_type translation_region,
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s32 translate_block_thumb(u32 pc, translation_region_type translation_region,
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u32 smc_enable);
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#if defined(PSP)
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4)
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#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024)
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#else
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4 * 5)
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#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384 * 2)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 32)
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#endif
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#define STUB_ARENA_SIZE (4*1024)
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#if defined(HAVE_MMAP)
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extern u8* rom_translation_cache;
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extern u8* ram_translation_cache;
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@ -147,8 +137,8 @@ extern int sceBlock;
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#else
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extern u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE];
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extern u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE];
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extern u32 stub_arena[STUB_ARENA_SIZE];
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#endif
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extern u32 stub_arena[STUB_ARENA_SIZE / 4];
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extern u8 *rom_translation_ptr;
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extern u8 *ram_translation_ptr;
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@ -162,9 +152,6 @@ extern u32 translation_gate_target_pc[MAX_TRANSLATION_GATES];
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extern u32 in_interrupt;
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#define ROM_BRANCH_HASH_SIZE (1024 * 64)
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/* EDIT: Shouldn't this be extern ?! */
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extern u32 *rom_branch_hash[ROM_BRANCH_HASH_SIZE];
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void flush_translation_cache_rom(void);
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@ -47,26 +47,10 @@ u8* ram_translation_cache_ptr;
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u8 *rom_translation_ptr = rom_translation_cache;
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u8 *ram_translation_ptr = ram_translation_cache;
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#else
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#ifdef __ANDROID__
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// Workaround for 'attempt to map x bytes at offset y'
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__asm__(".section .jit,\"awx\",%progbits");
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#else
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__asm__(".section .jit,\"awx\",%nobits");
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#endif
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u32 stub_arena[STUB_ARENA_SIZE]
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__attribute__ ((aligned(4),section(".jit")));
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u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE]
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__attribute__ ((aligned(4),section(".jit")));
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u8 *rom_translation_ptr = rom_translation_cache;
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u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE]
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__attribute__ ((aligned(4),section(".jit")));
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u8 *ram_translation_ptr = ram_translation_cache;
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__asm__(".section .text");
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#endif
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/* Note, see stub files for more cache definitions */
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u32 iwram_code_min = 0xFFFFFFFF;
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u32 iwram_code_max = 0xFFFFFFFF;
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@ -0,0 +1,22 @@
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#ifndef GPSP_CONFIG_H
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#define GPSP_CONFIG_H
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/* Cache sizes and their config knobs */
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#if defined(PSP)
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4)
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#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024)
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#else
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4 * 5)
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#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384 * 2)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 32)
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#endif
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/* This is MIPS specific for now */
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#define STUB_ARENA_SIZE (16*1024)
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/* Hash table size for ROM trans cache lookups */
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#define ROM_BRANCH_HASH_SIZE (1024 * 64)
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#endif
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@ -2618,11 +2618,7 @@ static void emit_mem_access_loadop(
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#define genccall(fn) mips_emit_jal(((u32)fn) >> 2);
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#endif
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// Stub memory map:
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// 0 .. 63 First patch handler [#0]
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// 448 .. 511 Last patch handler [#7]
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// 512+ smc_write handler
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#define SMC_WRITE_OFF32 160
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#define SMC_WRITE_OFF32 (10*16) /* 10 handlers (16 insts) */
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// Describes a "plain" memory are, that is, an area that is just accessed
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// as normal memory (with some caveats tho).
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@ -2862,8 +2858,7 @@ static void emit_pmemst_stub(
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}
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// If the data is non zero, we just wrote over code
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// Local-jump to the smc_write (which lives at offset:0)
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unsigned instoffset = (&stub_arena[SMC_WRITE_OFF32] - (((u32*)translation_ptr) + 1));
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mips_emit_b(bne, reg_zero, reg_temp, instoffset);
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mips_emit_b(bne, reg_zero, reg_temp, branch_offset(&stub_arena[SMC_WRITE_OFF32]));
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}
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// Store the data (delay slot from the SMC branch)
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@ -16,6 +16,8 @@
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#include "../gpsp_config.h"
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.set mips32r2
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.align 4
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@ -645,3 +647,22 @@ fnptrs:
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.long execute_spsr_restore_body # 6
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.long execute_store_cpsr_body # 7
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#if !defined(HAVE_MMAP)
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# Make this section executable!
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.text
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.section .jit,"awx",%nobits
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.align 2
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.global stub_arena
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.global rom_translation_cache
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.global ram_translation_cache
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stub_arena:
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.space STUB_ARENA_SIZE
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rom_translation_cache:
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.space ROM_TRANSLATION_CACHE_SIZE
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ram_translation_cache:
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.space RAM_TRANSLATION_CACHE_SIZE
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#endif
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@ -16,21 +16,18 @@
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#include "../gpsp_config.h"
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.align 4
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#define defsymbl(symbol) \
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.global symbol ; \
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.global _##symbol ; \
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symbol: \
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_##symbol:
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#ifndef _WIN32
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#define _x86_update_gba x86_update_gba
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#define _x86_indirect_branch_arm x86_indirect_branch_arm
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#define _x86_indirect_branch_thumb x86_indirect_branch_thumb
|
||||
#define _x86_indirect_branch_dual x86_indirect_branch_dual
|
||||
#define _execute_store_u8 execute_store_u8
|
||||
#define _execute_store_u16 execute_store_u16
|
||||
#define _execute_store_u32 execute_store_u32
|
||||
#define _execute_store_cpsr execute_store_cpsr
|
||||
#define _execute_arm_translate execute_arm_translate
|
||||
#define _memory_map_read memory_map_read
|
||||
#define _reg reg
|
||||
#define _reg_mode reg_mode
|
||||
# External symbols (data + functions)
|
||||
#define _oam_update oam_update
|
||||
#define _iwram iwram
|
||||
#define _ewram ewram
|
||||
|
|
@ -38,7 +35,6 @@
|
|||
#define _oam_ram oam_ram
|
||||
#define _bios_rom bios_rom
|
||||
#define _io_registers io_registers
|
||||
#define _spsr spsr
|
||||
|
||||
#define _update_gba update_gba
|
||||
#define _block_lookup_address_arm block_lookup_address_arm
|
||||
|
|
@ -47,8 +43,6 @@
|
|||
#define _write_io_register8 write_io_register8
|
||||
#define _write_io_register16 write_io_register16
|
||||
#define _write_io_register32 write_io_register32
|
||||
#define _palette_ram palette_ram
|
||||
#define _palette_ram_converted palette_ram_converted
|
||||
#define _flush_translation_cache_ram flush_translation_cache_ram
|
||||
#define _write_eeprom write_eeprom
|
||||
#define _write_backup write_backup
|
||||
|
|
@ -56,25 +50,7 @@
|
|||
#define _execute_store_cpsr_body execute_store_cpsr_body
|
||||
#endif
|
||||
|
||||
.global _x86_update_gba
|
||||
.global _x86_indirect_branch_arm
|
||||
.global _x86_indirect_branch_thumb
|
||||
.global _x86_indirect_branch_dual
|
||||
.global _execute_store_u8
|
||||
.global _execute_store_u16
|
||||
.global _execute_store_u32
|
||||
.global _execute_store_cpsr
|
||||
.global _execute_arm_translate
|
||||
|
||||
.global _memory_map_read
|
||||
.global _reg
|
||||
.global _reg_mode
|
||||
.global _spsr
|
||||
.global _palette_ram
|
||||
.global _palette_ram_converted
|
||||
|
||||
.global _oam_update
|
||||
|
||||
.global _iwram
|
||||
.global _ewram
|
||||
.global _vram
|
||||
|
|
@ -147,7 +123,7 @@
|
|||
st:
|
||||
.asciz "u\n"
|
||||
|
||||
_x86_update_gba:
|
||||
defsymbl(x86_update_gba)
|
||||
mov %eax, REG_PC(%ebx) # current PC = eax
|
||||
collapse_flags # update cpsr, trashes ecx and edx
|
||||
|
||||
|
|
@ -171,14 +147,14 @@ _x86_update_gba:
|
|||
# eax: GBA address to branch to
|
||||
# edi: Cycle counter
|
||||
|
||||
_x86_indirect_branch_arm:
|
||||
defsymbl(x86_indirect_branch_arm)
|
||||
call _block_lookup_address_arm
|
||||
jmp *%eax
|
||||
|
||||
# For indirect branches that'll definitely go to Thumb. In
|
||||
# Thumb mode any indirect branches except for BX.
|
||||
|
||||
_x86_indirect_branch_thumb:
|
||||
defsymbl(x86_indirect_branch_thumb)
|
||||
call _block_lookup_address_thumb
|
||||
jmp *%eax
|
||||
|
||||
|
|
@ -186,7 +162,7 @@ _x86_indirect_branch_thumb:
|
|||
# mainly BX (also data processing to PC with S bit set, be
|
||||
# sure to adjust the target with a 1 in the lowest bit for this)
|
||||
|
||||
_x86_indirect_branch_dual:
|
||||
defsymbl(x86_indirect_branch_dual)
|
||||
call _block_lookup_address_dual
|
||||
jmp *%eax
|
||||
|
||||
|
|
@ -297,7 +273,7 @@ ext_store_u8_jtable:
|
|||
# edx: value to write
|
||||
# ecx: current pc
|
||||
|
||||
_execute_store_u8:
|
||||
defsymbl(execute_store_u8)
|
||||
mov %ecx, REG_PC(%ebx) # write out the PC
|
||||
mov %eax, %ecx # ecx = address
|
||||
shr $24, %ecx # ecx = address >> 24
|
||||
|
|
@ -383,7 +359,7 @@ ext_store_u16_jtable:
|
|||
.long ext_store_eeprom # 0x0D EEPROM (possibly)
|
||||
.long ext_store_ignore # 0x0E Flash ROM/SRAM must be 8bit
|
||||
|
||||
_execute_store_u16:
|
||||
defsymbl(execute_store_u16)
|
||||
mov %ecx, REG_PC(%ebx) # write out the PC
|
||||
and $~0x01, %eax # fix alignment
|
||||
mov %eax, %ecx # ecx = address
|
||||
|
|
@ -400,6 +376,7 @@ ext_store_iwram32:
|
|||
and $0x7FFF, %eax # wrap around address
|
||||
mov %edx, (_iwram+0x8000)(%eax) # perform store
|
||||
cmpl $0, _iwram(%eax) # Check SMC mirror
|
||||
|
||||
jne smc_write
|
||||
ret
|
||||
|
||||
|
|
@ -456,7 +433,7 @@ ext_store_u32_jtable:
|
|||
.long ext_store_ignore # 0x0E Flash ROM/SRAM must be 8bit
|
||||
|
||||
|
||||
_execute_store_u32:
|
||||
defsymbl(execute_store_u32)
|
||||
mov %ecx, REG_PC(%ebx) # write out the PC
|
||||
and $~0x03, %eax # fix alignment
|
||||
mov %eax, %ecx # ecx = address
|
||||
|
|
@ -470,7 +447,7 @@ _execute_store_u32:
|
|||
# %eax = new_cpsr
|
||||
# %edx = store_mask
|
||||
|
||||
_execute_store_cpsr:
|
||||
defsymbl(execute_store_cpsr)
|
||||
mov %edx, REG_SAVE(%ebx) # save store_mask
|
||||
mov %ecx, REG_SAVE2(%ebx) # save PC too
|
||||
|
||||
|
|
@ -515,7 +492,7 @@ lookup_pc_arm:
|
|||
|
||||
# eax: cycle counter
|
||||
|
||||
_execute_arm_translate:
|
||||
defsymbl(execute_arm_translate)
|
||||
# Save main context, since we need to return gracefully
|
||||
pushl %ebx
|
||||
pushl %esi
|
||||
|
|
@ -556,18 +533,30 @@ return_to_main:
|
|||
.data
|
||||
.align 64
|
||||
|
||||
_reg:
|
||||
defsymbl(reg)
|
||||
.space 0x100, 0
|
||||
_palette_ram:
|
||||
defsymbl(palette_ram)
|
||||
.space 0x400
|
||||
_palette_ram_converted:
|
||||
defsymbl(palette_ram_converted)
|
||||
.space 0x400
|
||||
_spsr:
|
||||
defsymbl(spsr)
|
||||
.space 24
|
||||
_reg_mode:
|
||||
defsymbl(reg_mode)
|
||||
.space 196
|
||||
|
||||
_memory_map_read:
|
||||
defsymbl(memory_map_read)
|
||||
.space 0x8000
|
||||
|
||||
#if !defined(HAVE_MMAP)
|
||||
|
||||
# Make this section executable!
|
||||
.text
|
||||
.section .jit,"awx",%nobits
|
||||
.align 4
|
||||
defsymbl(rom_translation_cache)
|
||||
.space ROM_TRANSLATION_CACHE_SIZE
|
||||
defsymbl(ram_translation_cache)
|
||||
.space RAM_TRANSLATION_CACHE_SIZE
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue