Commit Graph

428 Commits

Author SHA1 Message Date
Autechre b9ac453675
Merge pull request #109 from jdgleaver/post-process-fix
Ensure post processing configuration is correctly reset in retro_deinit()
2021-03-16 14:24:29 +01:00
jdgleaver 3db8eba7fd Ensure post processing configuration is correctly reset in retro_deinit() 2021-03-16 13:14:21 +00:00
Autechre 9551d76484
Merge pull request #108 from davidgfnet/master
Move a few more registers to context
2021-03-16 02:09:41 +01:00
David Guillen Fandos 46cad2958a Move a few more registers to context
This gets rid of some more absolute addrs in the MIPS dynarec.
Tested on several platforms, we should be good.
2021-03-16 01:02:10 +01:00
Autechre bfc7cc7fdf
Merge pull request #107 from davidgfnet/master
Move palettes around to simplify MIPS dynarec
2021-03-15 02:33:30 +01:00
David Guillen Fandos c86b9064df Move palettes around to simplify MIPS dynarec
Will move also OAM structures to gain a few cycles per load/store.
Loads can also be optimized for an extra instruction per access.
2021-03-15 02:25:02 +01:00
Autechre 6e9104e1ee
Merge pull request #105 from davidgfnet/master
Fix typo
2021-03-12 23:19:10 +01:00
David Guillen Fandos 1f63b39523 Fix typo 2021-03-12 23:15:03 +01:00
Autechre 8d60fb2507
Merge pull request #104 from davidgfnet/master
Improve and simplify dynarec JIT area.
2021-03-12 22:36:33 +01:00
David Guillen Fandos 1e8097ac79 Improve and simplify dynarec JIT area.
Also fix a regression on VITA.
Use gcc/OS cache flushing routines for MIPS32 instead of synci
2021-03-12 18:05:48 +01:00
Autechre e178b25425
Merge pull request #103 from davidgfnet/cachestuff
Improve cache flush magic
2021-03-12 05:35:17 +01:00
Autechre 7d25898439
Merge pull request #102 from davidgfnet/master
Remove PSP-specific stuff from MIPS backend
2021-03-12 01:52:53 +01:00
David Guillen Fandos 462f0e9784 Improve cache flush magic
Make it better and more generic. Add support for MIPS32 and fix the
messy PSP code.
2021-03-12 01:46:09 +01:00
David Guillen Fandos 7db08a3fcf Fix fd check 2021-03-11 22:13:32 +01:00
David Guillen Fandos 5127f4b5cc Remove PSP-specific stuff from MIPS backend
This is unnecessary since newlib supports all file I/O.
This is needed for other mips ports
2021-03-10 18:41:37 +01:00
twinaphex bd36c9c77d Add osx-arm64 target 2021-03-09 22:05:36 +01:00
Autechre 45c8ef0a0b
Merge pull request #101 from davidgfnet/master
Remove libco
2021-03-09 20:31:50 +01:00
David Guillen Fandos 0522d9a4f5 Add workaround for Android ARM builds
While we are at it, use ARM mode for better performance.
2021-03-09 19:29:18 +01:00
twinaphex 6a8aa84200 Add ios-arm64/tvos-arm64 2021-03-09 04:45:35 +01:00
David Guillen Fandos 56dc6ecb70 Remove libco
This removes libco and all the usages of it (+pthreads).
Rewired all dynarecs and interpreter to return after every frame so that
libretro can process events. This required to make dynarec re-entrant.

Dynarecs were updated to check for new frame on every update (IRQ, cycle
exhaustion, I/O write, etc). The performance impact of doing so should
be minimal (and definitely outweight the libco gains). While at it,
fixed small issues to get a bit more perf: arm dynarec was not idling
correctly, mips was using stack when not needed, etc.

Tested on PSP (mips), OGA (armv7), Linux (x86 and interpreter). Not
tested on Android though.
2021-03-08 18:44:03 +01:00
Autechre d1b8c2d92b
Merge pull request #100 from davidgfnet/master
Fix a ghost bug with some games
2021-03-08 03:02:50 +01:00
David Guillen Fandos 02e35339ee Fix a ghost bug with some games
Affects at least SM Adv 4 on PSP, which doesn't load at all.
I think the MIPS pipeline does not like invalidating the Icache and
using it immediately after (seems to read an old value sometimes?).
Rewired it to not do that and instead jump to the handler directly.
2021-03-08 02:59:11 +01:00
Autechre 7fcd1e5e30
Merge pull request #99 from davidgfnet/master
Fix x86 dynarec, broken by d10c4afe
2021-03-06 21:23:42 +01:00
David Guillen Fandos 3d558413fd Fix x86 dynarec, broken by d10c4afe
The dynarec expects function args to be located in registers instead of
the stack, which is not the default calling convetion in GCC/clang.
2021-03-06 21:15:22 +01:00
Autechre cbcb5df7da
Merge pull request #98 from davidgfnet/master
ARM dynarec: Do not use the stack at all
2021-03-05 18:27:13 +01:00
David Guillen Fandos d21478e06e ARM dynarec: Do not use the stack at all
Fix a C func call while at it. This is a prerequisite to make the
dynarec re-entrant and get rid of libco
2021-03-05 17:47:20 +01:00
Autechre fa45d3701a
Merge pull request #97 from davidgfnet/master
Minor ARM cleanup
2021-03-05 04:54:57 +01:00
David Guillen Fandos 7bebd3051c Remove dead code
Turns out this was not even used! No need to fix it then!
2021-03-05 01:15:55 +01:00
David Guillen Fandos 89bd699837 Reduce executable size by 90%
Turns out most of that file ends up in JIT section, which is RWX and not
a very nice way to run code really (security issues aside).
This also makes possible to build that file with -ggdb otherwise it
complains about stuff.
2021-03-05 01:14:31 +01:00
Autechre 1e8a6328ff
Merge pull request #96 from davidgfnet/master
Minor improvements in ARM stubs
2021-03-04 18:56:58 +01:00
David Guillen Fandos 6770e0a5e7 Minor improvements in ARM stubs
This gets rid of stack usage (except for callback invocations) in the
dynarec execution code. A requirement to make the dynarec re-entrant.
2021-03-04 18:35:48 +01:00
Autechre a78ef12b82
Merge pull request #95 from davidgfnet/master
Remove more dead code
2021-02-26 19:21:59 +01:00
David Guillen Fandos f6ead0812a Remove more dead code 2021-02-26 18:36:57 +01:00
Autechre 28aa08de99
Merge pull request #94 from davidgfnet/master
Small fixes to division by zero
2021-02-24 03:58:08 +01:00
David Guillen Fandos 349e47f0b2 Small fixes to division by zero
This causes crashes in PSP quite often in many games. Other CPUs might
(depending on the processor state) silently return zero or some
undefined value.
The fix is borrowed from ReGBA's codebase
2021-02-23 20:27:59 +01:00
Autechre 300d0c0028
Merge pull request #93 from davidgfnet/master
More cleanups (mostly whitespace and unused stuff)
2021-02-15 22:30:27 +01:00
David Guillen Fandos ed3ba2c18b More cleanups (mostly whitespace and unused stuff) 2021-02-15 21:51:49 +01:00
Autechre fa74054508
Merge pull request #92 from davidgfnet/master
Minor cleanup in ARM and MIPS
2021-02-13 02:01:10 +01:00
David Guillen Fandos 8d52e613c7 Minor cleanup in ARM and MIPS
Fix some small issues, mainly associated with undefined behaviour
expressions
2021-02-12 21:47:35 +01:00
Autechre 6254bbb1d2
Merge pull request #91 from davidgfnet/master
Fix ARM dynarec
2021-02-10 10:35:56 +01:00
David Guillen Fandos 2c6026cfe5 Move r15 to reg_a0 (instead of reg_mem)
I think this does not make a difference at all in the code, since PC is
treated in a special way anyway (reloaded with an immediate when read
and treated as an indirect branch when written). However for the sake of
completeness I'm undoing what I did. (The comma fix stays :P)
2021-02-10 02:53:26 +01:00
David Guillen Fandos 7aaa280b9f Fix ARM dynarec
Turns out there were a couple of very interesting and hard to track
bugs. A missing comma made the reg list too short, leaving the 31th
element at the mercy of the linker ordering algorithm, which seems to
work in some cases depending on the compiler version.
Also the cache flush code seemed not to work on my machine (OGA),
not sure why it wored in the past :/
2021-02-10 02:46:45 +01:00
twinaphex f70d8534a1 Fix libco for arm64 2021-01-27 13:17:24 +01:00
Autechre 2b6f1d552e
Update .gitlab-ci.yml 2021-01-09 17:03:57 +01:00
Autechre d8e0790ce9
Update .gitlab-ci.yml 2021-01-09 16:40:28 +01:00
Autechre f520876ef6
Update .gitlab-ci.yml 2021-01-03 01:10:16 +01:00
twinaphex 23b2a55f0d Update 2020-12-19 23:18:41 +01:00
twinaphex 1d803fbdd9 Update 2020-12-06 20:25:38 +01:00
twinaphex 99e35c642c Update .gitlab-ci.yml 2020-12-06 19:45:23 +01:00
jdgleaver e4745d32ec Add 3DS target to .gitlab-ci.yml 2020-12-03 14:05:54 +01:00