Autechre
GitHub
commit
a78ef12b82
297
psp/mips_stub.S
297
psp/mips_stub.S
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@ -2471,12 +2471,6 @@ patch_store_u32a:
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patch_handler store_u32a_ftable, 0x0F
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# General ext memory routines
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ext_store_ignore:
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jr $ra # ignore these writes
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nop
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write_io_epilogue:
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beq $2, $0, no_alert # 0 means nothing happened
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addiu $4, $2, -2 # see if return value is 2 (delay slot)
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@ -2487,6 +2481,8 @@ write_io_epilogue:
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nop
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collapse_flags # make sure flags are good for update_gba
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alert_loop:
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jal update_gba # process the next event
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nop
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@ -2518,295 +2514,6 @@ smc_dma:
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j lookup_pc
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nop
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ext_store_eeprom:
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addiu $sp, $sp, -4 # make room on the stack for $ra
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sw $ra, ($sp)
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save_registers
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jal write_eeprom # write the value out
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sw $6, REG_PC($16) # save the PC (delay slot)
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restore_registers
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lw $ra, ($sp) # restore return address
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jr $ra # we can return
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addiu $sp, $sp, 4 # fix the stack
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# 8bit ext memory routines
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ext_store_io8:
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andi $5, $5, 0xFF # make value 8bit
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andi $4, $4, 0x3FF # wrap around address
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addiu $sp, $sp, -4 # make room on the stack for $ra
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sw $ra, ($sp)
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save_registers
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jal write_io_register8 # write the value out
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sw $6, REG_PC($16) # save the PC (delay slot)
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j write_io_epilogue # handle any state changes
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nop
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ext_store_palette8:
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j ext_store_palette16b # perform 16bit palette write
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andi $4, $4, 0x3FE # wrap + align (delay)
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ext_store_vram8:
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ins $5, $5, 8, 8 # value = (value << 8) | value
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ext $4, $4, 0, 17 # address = adress & 0x1FFFF
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ins $4, $0, 0, 1 # align out bottom bit
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lui $1, %hi(0x18000) # $1 = 0x18000
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sltu $1, $4, $1 # see if address < 0x18000
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bne $1, $0, ext_store_vram8b
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lui $2, %hi(vram) # start loading vram address (delay)
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addiu $4, $4, -0x8000 # move address into VRAM region
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ext_store_vram8b:
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addu $2, $2, $4 # $2 = (hi)vram + address
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jr $ra # return
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sh $5, %lo(vram)($2) # vram[address] = value (delay)
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ext_store_oam8:
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lui $1, %hi(oam_update) # $1 = oam_update
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addiu $1, %lo(oam_update)
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li $2, 1 # $2 = 1
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sw $2, ($1) # *oam_update = 1
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andi $4, $4, 0x3FE # wrap around address and align to 16bits
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ins $5, $5, 8, 8 # value = (value << 8) | value
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lui $1, %hi(oam_ram) # $1 = (hi)oam_ram
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addu $1, $1, $4 # $1 = (hi)oam_ram + address
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jr $ra # return
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sh $5, %lo(oam_ram)($1) # oam_ram[address] = value (delay)
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ext_store_backup:
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andi $5, $5, 0xFF # make value 8bit
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andi $4, $4, 0xFFFF # mask value
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addiu $sp, $sp, -4 # make room on the stack for $ra
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sw $ra, ($sp)
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save_registers
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jal write_backup # write the value out
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sw $6, REG_PC($16) # save the PC (delay slot)
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restore_registers
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lw $ra, ($sp) # restore return address
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jr $ra # we can return
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addiu $sp, $sp, 4 # fix the stack
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ext_store_u8_jtable:
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.long ext_store_ignore # 0x00 BIOS
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.long ext_store_ignore # 0x01 invalid
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.long ext_store_ignore # 0x02 EWRAM
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.long ext_store_ignore # 0x03 IWRAM
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.long ext_store_io8 # 0x04 I/O registers
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.long ext_store_palette8 # 0x05 Palette RAM
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.long ext_store_vram8 # 0x06 VRAM
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.long ext_store_oam8 # 0x07 OAM RAM
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.long ext_store_ignore # 0x08 gamepak (no RTC accepted in 8bit)
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.long ext_store_ignore # 0x09 gamepak, ignore
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.long ext_store_ignore # 0x0A gamepak, ignore
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.long ext_store_ignore # 0x0B gamepak, ignore
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.long ext_store_ignore # 0x0C gamepak, ignore
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.long ext_store_eeprom # 0x0D EEPROM (possibly)
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.long ext_store_backup # 0x0E Flash ROM/SRAM
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.long ext_store_ignore # 0x0F invalid
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# 16bit ext memory routines
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ext_store_io16:
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andi $4, $4, 0x3FF # wrap around address
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andi $5, $5, 0xFFFF # make value 16bit
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addiu $sp, $sp, -4 # make room on the stack for $ra
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sw $ra, ($sp)
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save_registers
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jal write_io_register16 # write the value out
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sw $6, REG_PC($16) # save the PC (delay slot)
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j write_io_epilogue # handle any state changes
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nop
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ext_store_palette16:
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andi $4, 0x3FF # wrap address
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ext_store_palette16b:
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lui $2, %hi(palette_ram)
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addu $2, $2, $4
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sh $5, %lo(palette_ram)($2) # palette_ram[address] = value
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sll $1, $5, 1 # make green 6bits
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ins $1, $0, 0, 6 # make bottom bit 0
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ins $1, $5, 0, 5 # insert red channel into $1
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lui $2, %hi(palette_ram_converted)
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addu $2, $2, $4
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jr $ra # return
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sh $1, %lo(palette_ram_converted)($2)
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ext_store_vram16:
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ext $4, $4, 0, 17 # address = adress & 0x1FFFF
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lui $1, %hi(0x18000) # $1 = 0x18000
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sltu $1, $4, $1 # see if address < 0x18000
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bne $1, $0, ext_store_vram16b
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lui $2, %hi(vram) # start loading vram address (delay)
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addiu $4, $4, -0x8000 # move address into VRAM region
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ext_store_vram16b:
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addu $2, $2, $4 # $2 = (hi)vram + address
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jr $ra # return
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sh $5, %lo(vram)($2) # vram[address] = value (delay)
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ext_store_oam16:
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lui $1, %hi(oam_update) # $1 = oam_update
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addiu $1, %lo(oam_update)
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li $2, 1 # $2 = 1
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sw $2, ($1) # *oam_update = 1
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andi $4, $4, 0x3FF # wrap around address
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lui $1, %hi(oam_ram) # $1 = (hi)oam_ram
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addu $1, $1, $4 # $1 = (hi)oam_ram + address
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jr $ra # return
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sh $5, %lo(oam_ram)($1) # oam_ram[address] = value (delay)
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ext_store_rtc:
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andi $5, $5, 0xFFFF # make value 16bit
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addiu $sp, $sp, -4 # make room on the stack for $ra
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sw $ra, ($sp)
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save_registers
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jal write_rtc # write the value out
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sw $6, REG_PC($16) # save the PC (delay slot)
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restore_registers
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lw $ra, ($sp) # restore return address
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jr $ra # we can return
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addiu $sp, $sp, 4 # fix the stack
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ext_store_u16_jtable:
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.long ext_store_ignore # 0x00 BIOS, ignore
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.long ext_store_ignore # 0x01 invalid, ignore
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.long ext_store_ignore # 0x02 EWRAM, should have been hit already
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.long ext_store_ignore # 0x03 IWRAM, should have been hit already
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.long ext_store_io16 # 0x04 I/O registers
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.long ext_store_palette16 # 0x05 Palette RAM
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.long ext_store_vram16 # 0x06 VRAM
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.long ext_store_oam16 # 0x07 OAM RAM
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.long ext_store_rtc # 0x08 gamepak, RTC
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.long ext_store_ignore # 0x09 gamepak, ignore
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.long ext_store_ignore # 0x0A gamepak, ignore
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.long ext_store_ignore # 0x0B gamepak, ignore
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.long ext_store_ignore # 0x0C gamepak, ignore
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.long ext_store_eeprom # 0x0D EEPROM (possibly)
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.long ext_store_ignore # 0x0E Flash ROM/SRAM
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# 32bit ext memory routines
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ext_store_io32:
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andi $4, $4, 0x3FF # wrap around address
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addiu $sp, $sp, -4 # make room on the stack for $ra
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sw $ra, ($sp)
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save_registers
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jal write_io_register32 # write the value out
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sw $6, REG_PC($16) # save the PC (delay slot)
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j write_io_epilogue # handle any state changes
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nop
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ext_store_palette32:
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addu $6, $ra, $0 # save return address in $6
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jal ext_store_palette16b # write out palette entry
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andi $4, 0x3FF # wrap address (delay)
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addiu $4, $4, 2 # go to next location
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srl $5, $5, 16 # shift to next 16bit value
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j ext_store_palette16b # write out next palette entry
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addu $ra, $6, $0 # restore return address (delay)
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ext_store_vram32:
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ext $4, $4, 0, 17 # address = adress & 0x1FFFF
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lui $1, %hi(0x18000) # $1 = 0x18000
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sltu $1, $4, $1 # see if address < 0x18000
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bne $1, $0, ext_store_vram32b
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lui $2, %hi(vram) # start loading vram address (delay)
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addiu $4, $4, -0x8000 # move address into VRAM region
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ext_store_vram32b:
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addu $2, $2, $4 # $2 = (hi)vram + address
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jr $ra # return
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sw $5, %lo(vram)($2) # vram[address] = value (delay)
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ext_store_oam32:
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lui $1, %hi(oam_update) # $1 = oam_update
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addiu $1, %lo(oam_update)
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li $2, 1 # $2 = 1
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sw $2, ($1) # *oam_update = 1
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andi $4, $4, 0x3FF # wrap around address
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lui $1, %hi(oam_ram) # $1 = (hi)oam_ram
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addu $1, $1, $4 # $1 = (hi)oam_ram + address
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jr $ra # return
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sw $5, %lo(oam_ram)($1) # oam_ram[address] = value (delay)
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ext_store_u32_jtable:
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.long ext_store_ignore # 0x00 BIOS, ignore
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.long ext_store_ignore # 0x01 invalid, ignore
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.long ext_store_ignore # 0x02 EWRAM, should have been hit already
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.long ext_store_ignore # 0x03 IWRAM, should have been hit already
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.long ext_store_io32 # 0x04 I/O registers
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.long ext_store_palette32 # 0x05 Palette RAM
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.long ext_store_vram32 # 0x06 VRAM
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.long ext_store_oam32 # 0x07 OAM RAM
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.long ext_store_ignore # 0x08 gamepak, ignore
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.long ext_store_ignore # 0x09 gamepak, ignore
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.long ext_store_ignore # 0x0A gamepak, ignore
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.long ext_store_ignore # 0x0B gamepak, ignore
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.long ext_store_ignore # 0x0C gamepak, ignore
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.long ext_store_eeprom # 0x0D EEPROM (possibly)
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.long ext_store_ignore # 0x0E Flash ROM/SRAM
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ext_store_u32:
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srl $1, $4, 24 # $1 = address >> 24
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sltu $2, $1, 16 # check if the value is out of range
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beq $2, $0, ext_store_ignore
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sll $1, $1, 2 # make address word indexed (delay)
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lui $2, %hi(ext_store_u32_jtable)
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addu $2, $2, $1
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# $2 = ext_store_u32_jtable[address >> 24]
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lw $2, %lo(ext_store_u32_jtable)($2)
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jr $2 # jump to table location
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nop
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# 32bit ext aligned, non a2 destroying routines
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ext_store_io32a:
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andi $4, $4, 0x3FF # wrap around address
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addiu $sp, $sp, -4 # make room on the stack for $ra
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sw $ra, ($sp)
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save_registers
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jal write_io_register32 # write the value out
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sw $6, REG_SAVE($16) # save a2
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lw $6, REG_SAVE($16) # restore a2
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j write_io_epilogue # handle any state changes
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nop
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ext_store_palette32a:
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sw $ra, REG_SAVE($16) # save return address
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jal ext_store_palette16b # write out palette entry
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andi $4, 0x3FF # wrap address (delay)
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addiu $4, $4, 2 # go to next location
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srl $5, $5, 16 # shift to next 16bit value
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j ext_store_palette16b # write out next palette entry
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lw $ra, REG_SAVE($16) # restore return address (delay)
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ext_store_u32a_jtable:
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.long ext_store_ignore # 0x00 BIOS, ignore
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.long ext_store_ignore # 0x01 invalid, ignore
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.long ext_store_ignore # 0x02 EWRAM, should have been hit already
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.long ext_store_ignore # 0x03 IWRAM, should have been hit already
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.long ext_store_io32a # 0x04 I/O registers
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.long ext_store_palette32a # 0x05 Palette RAM
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.long ext_store_vram32 # 0x06 VRAM
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.long ext_store_oam32 # 0x07 OAM RAM
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.long ext_store_ignore # 0x08 gamepak, ignore
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.long ext_store_ignore # 0x09 gamepak, ignore
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.long ext_store_ignore # 0x0A gamepak, ignore
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.long ext_store_ignore # 0x0B gamepak, ignore
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.long ext_store_ignore # 0x0C gamepak, ignore
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.long ext_store_ignore # 0x0D EEPROM (nothing will write this)
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.long ext_store_ignore # 0x0E Flash ROM/SRAM
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smc_write:
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save_registers
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jal flush_translation_cache_ram # flush translation cache
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