Commit Graph

604 Commits

Author SHA1 Message Date
David Guillen Fandos e8eb753a73 [mips] Minor cleanup and remove a couple of nested functions 2021-11-06 22:31:42 +01:00
David Guillen Fandos 92180d5d7e Minor unused stuff cleanup 2021-11-06 21:49:08 +01:00
David Guillen Fandos c0804fa48d [x64] Enable Android x86-64 support (not tested!) 2021-11-06 12:39:16 +01:00
David Guillen Fandos aa52f960c8 Fix Makefile arch detection support
x86/64 detection only enabled for unix platforms, since other platforms
have hardcoded rules (including windows).
2021-11-06 12:32:20 +01:00
David Guillen Fandos e3d5ca8419 [x86/x64] Add support for x86-64 and improve 32 bit mode too.
This adds support for x86-64 dynarec both on Windows and Linux. Since
they have different requirements there's some macro magic in the stubs
file.

This also fixes x86 support in some cases: stack alignment requirements
where violated all over. This allows the usage of clang as a compiler
(which has a tendency to use SSE instructions more often than gcc does).

To support this I also reworked the mmap/VirtualAlloc magic to make sure
JIT arena stays close to .text.

Fixed some other minor issues and removed some unnecessary JIT code here
and there. clang tends to do some (wrong?) assumptions about global
symbols alignment.
2021-11-06 12:17:50 +01:00
David Guillen Fandos d63fea580c Oops printf there! 2021-11-05 23:15:08 +01:00
David Guillen Fandos 3a7fedb8fb Simplify MMAP machinery for Win/Lin/Mac/Android
This gets rid of the bloated memmap_win32.c in favour of a much simpler
wrapper. This will be needed in the future since the wrapper does not
support MAP_FIXED maps (necessary for some platforms)
2021-11-05 18:23:05 +01:00
David Guillen Fandos 3368ad6f8e Remove broken fpic strip 2021-11-05 17:52:22 +01:00
David Guillen Fandos 09a7afe216 [x86] Remove usage of esi register 2021-11-04 20:31:50 +01:00
David Guillen Fandos dee9a6ed36 [MIPS] Fix swap implementation
No game seems to use this :P
2021-11-04 20:09:05 +01:00
David Guillen Fandos fc55198b76 [x86] Implement load handlers in asm stubs for speed 2021-11-03 22:20:31 +01:00
David Guillen Fandos 44ccdb3d25 Minor mem handler fixes (pretty much a no-op) 2021-11-03 21:33:29 +00:00
David Guillen Fandos 746503af95 [x86] Consolidate mem writes 2021-11-02 23:16:47 +01:00
David Guillen Fandos 9c99a918d0 Minor macro cleanups 2021-11-02 22:00:09 +01:00
David Guillen Fandos 6f81dbad1d Minor code cleanup to make it more readable 2021-11-02 21:14:38 +01:00
David Guillen Fandos 0d864be803 Simplify PSR stores for x86. Use only 2 function args 2021-11-02 21:02:05 +01:00
David Guillen Fandos 4d0d8dc42d [x86] Move reg_cycles to EBP, for better compatiblity 2021-11-02 20:11:46 +01:00
David Guillen Fandos 15cc02e03c [MIPS] Move and restructure mips backend 2021-10-30 22:59:33 +02:00
David Guillen Fandos 3f012afcda Make ROM hash table mechanism 64 bit compatible. 2021-10-30 22:54:51 +02:00
David Guillen Fandos c39f5391f0 [ARM] Start using mmap'ed JIT caches for most builds
Will revisit remaining platforms and try to clean them too.
This should fix Android once and for all.
2021-10-29 22:51:39 +02:00
David Guillen Fandos 5c1467cb63 [ARM] Remove cross calls between cache and text (far calls)
This is to allow cache to be mapped far from the regular .text section
2021-10-29 22:34:29 +02:00
David Guillen Fandos f65c3939b5 [ARM] Rewrite HLE emulation for div, make it faster and simpler.
Moves the handlers to the cache, removes C usage.
2021-10-24 18:00:06 +02:00
David Guillen Fandos b65df123f8 [ARM] Add support for ARMv5 2021-10-23 23:59:51 +02:00
David Guillen Fandos d558fb4fc4 [ARM] Rework memory handlers for speed amb simplicity
This removes one branch and emits the region selection code directly in
the JIT cache. Trading memory for speed (although it's not a big
improvement).

This is a step towards enabling MMAP caches in ARM (due to the 32MB
offset limitation in branches).
2021-10-23 23:33:15 +02:00
David Guillen Fandos 4bebb6135d Inline spsr operations 2021-10-23 12:02:46 +02:00
David Guillen Fandos d89977d25d Fix CPSR reads in ARM32
Interestingly enough, doesn't seem to affect more than a couple games.
2021-10-23 09:31:21 +02:00
David Guillen Fandos cdb61227bc Fix arm32 spsr writes: only write selected bits
Seems no game is affected, even though the current implementration is
broken. Most games seem to not use mask at all.
2021-10-23 09:06:24 +02:00
David Guillen Fandos 8da094d7e0 Add 60FPS overclock hack
Let's see, this should fix issues on platforms that do not support
running the emu at 59.73 FPS. We run the emu at fake 60fps, which means
we produce more audio samples than the original device.

Instead of missing samples (which produce cracks in the audio) we should
be producing some extra samples, which will result in a frame drop every
now and then (like every minute or so, so it's not noticeable).
2021-10-20 01:15:40 +02:00
David Guillen Fandos 6a59c71d55 Get rid of enums (to u32) for better compat
Serialization code needs u32 to ensure compatiblity. In platforms with
short enums this goes very wrong. Fixes issues on 3DS platform.
2021-10-15 21:28:40 +02:00
twinaphex bd5cf7c1e5 Fix header includes 2021-09-30 23:30:03 +02:00
David Guillen Fandos 6c195cdcaa Add libretro-common and VFS functions for read/write
Remove small unused stuff while at it.
2021-09-30 18:31:11 +02:00
David Guillen Fandos 4dc706f361 Improve flag shifts (MIPS) 2021-09-25 23:26:08 +02:00
David Guillen Fandos 9abb3ef934 Add printf flush to better capture crashes 2021-09-19 21:50:38 +02:00
David Guillen Fandos b7472eedf1 Add EOB translation gate to fix blocks that are too big
This fixes a couple of games only (AFAICS)
2021-09-19 21:35:13 +02:00
David Guillen Fandos 3cab8596b8 Fix SWI handling (disable IRQs)
This introduced a potential race condition between the start of a SWI
and the BIOS handling the exception by returning to system mode. During
this ~10 instruction window, having an IRQ that issues a SWI causes bad
behaviour that results in crashes or other weirdness.
Fixes a couple of games and potentially many weird and obscure bugs here
and there (hard to reproduce sometimes).
2021-09-17 22:22:01 +02:00
David Guillen Fandos ed89923fda Minor mem fixes around mirrors and u8/u16 accesses
Improve the open bus access a bit too.
2021-09-17 21:30:33 +02:00
David Guillen Fandos 8fabfaf2a8 Fix shift by register in interpreter
Only the LSB byte is actually used.
2021-09-17 20:17:51 +02:00
David Guillen Fandos c2c2564e4a Simplify help functions in x86 backend 2021-09-17 20:00:37 +02:00
David Guillen Fandos 1eaf700ff6 Simplify conditional branches in x86
Make them more efficient while at it
2021-09-17 19:18:50 +02:00
David Guillen Fandos 9b0d685092 Fix divide by zero in the x86 BIOS HLE
Fixes ~10 games that divide zero by zero
2021-09-16 19:30:30 +02:00
David Guillen Fandos 401adca6ae Cleanup unused stuff in mips and arm 2021-09-15 20:34:21 +02:00
David Guillen Fandos 33f1e25099 Emit BIOS SWI entrypoint to ROM arena
This fixes a race condition that happens whenever the ROM cache is flushed but
the RAM one is not, causing any SWI calls (implemented as direct branches) to
jump to random instructions.
The fix could be to flush both caches at the same time (~expensive on
low mem platforms), use indirect jumps (a bit expensive) or emit the SWI
handler below the watermark to ensure it is never flushed. This is cheap
and effective, requires minimal changes.
2021-09-10 00:30:55 +02:00
David Guillen Fandos b431a8a4b6 Merge stub arena into ROM cache for simplicity. 2021-09-09 19:06:15 +02:00
David Guillen Fandos 663767b078 Checking in Normatt's BIOS source code for reference and development. 2021-09-07 00:28:31 +02:00
David Guillen Fandos ad6bf7f24a Minor x86 edits 2021-09-03 18:51:57 +02:00
David Guillen Fandos f51ed9de13 Improve SWI codepaths and implement div&divarm natively 2021-09-03 01:01:37 +02:00
David Guillen Fandos e0708b1dcf x86: Simplify thumb instructions and remove last function calls 2021-09-01 19:34:43 +02:00
David Guillen Fandos 8dda395c54 Implement asr/lsl/ror/lsr operand2 natively
This gives some small perf bump
2021-08-31 21:18:22 +02:00
David Guillen Fandos 66e011b0a3 Write most alu/log x86 operations as emitted code
This is around 8% perf improvement alone.
This also fixes many flag calculation/usage bugs (in corner cases) since
we use the x86 cpu native ALU flags (which are more or less the same as
ARM's). Passes all test ROMs for ALUs and no changes in game compat.
2021-08-31 00:42:47 +02:00
David Guillen Fandos 2295dc4a3a Fix bad ARM code emitter bug
This mis-emits CMN instead of TEQ and TST in the reg-shift operand mode.
This is never used by gpsp directly but translating real tst opcodes,
hence it only affects games using such instruction.

This fixes video players that previously crashed, many games that had
graphical glitches in ARM mode (but not on other CPUs) usually in menus
or other dialogues. Also fixes games that either crashed or went blank
or similar issues. The extent of fixing is hard to determine but could
affect many games in different levels.
2021-08-30 02:07:31 +02:00