[x86] Remove usage of esi register
This commit is contained in:
David Guillen Fandos
parent
dee9a6ed36
commit
09a7afe216
1 changed files with 32 additions and 27 deletions
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@ -401,8 +401,8 @@ typedef enum
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#define reg_a0 eax
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#define reg_a1 edx
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#define reg_a2 ecx
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#define reg_t0 esi
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#define reg_rv eax
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#define reg_s0 esi // Any saved register
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/* Offsets from reg_base, see stub.S */
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#define SPSR_BASE_OFF 0xA9100
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@ -1313,18 +1313,18 @@ u32 function_cc execute_spsr_restore(u32 address)
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} \
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#define arm_multiply_long_flags_yes() \
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generate_mov(s0, a1); \
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generate_and(s0, s0); \
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generate_mov(t0, a1); \
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generate_and(t0, t0); \
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generate_update_flag(s, REG_N_FLAG) \
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generate_or(s0, a0); \
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generate_or(t0, a0); \
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generate_update_flag(z, REG_Z_FLAG) \
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#define arm_multiply_long_flags_no(_dest) \
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#define arm_multiply_long_add_yes(name) \
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generate_load_reg(a2, rdlo); \
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generate_load_reg(s0, rdhi); \
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generate_multiply_##name(a1, a2, s0) \
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generate_load_reg(t0, rdhi); \
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generate_multiply_##name(a1, a2, t0) \
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#define arm_multiply_long_add_no(name) \
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generate_multiply_##name(a1) \
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@ -1523,15 +1523,15 @@ u32 function_cc execute_store_cpsr_body(u32 _cpsr)
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} \
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#define arm_block_memory_offset_down_a() \
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generate_add_imm(s0, -((word_bit_count(reg_list) * 4) - 4)) \
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generate_add_imm(a0, -((word_bit_count(reg_list) * 4) - 4)) \
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#define arm_block_memory_offset_down_b() \
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generate_add_imm(s0, -(word_bit_count(reg_list) * 4)) \
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generate_add_imm(a0, -(word_bit_count(reg_list) * 4)) \
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#define arm_block_memory_offset_no() \
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#define arm_block_memory_offset_up() \
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generate_add_imm(s0, 4) \
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generate_add_imm(a0, 4) \
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#define arm_block_memory_writeback_down() \
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generate_load_reg(a0, rn) \
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@ -1562,17 +1562,19 @@ u32 function_cc execute_store_cpsr_body(u32 _cpsr)
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u32 offset = 0; \
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u32 i; \
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\
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generate_load_reg(s0, rn); \
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generate_load_reg(a0, rn); \
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arm_block_memory_offset_##offset_type(); \
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generate_and_imm(a0, ~0x03); \
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generate_store_reg(a0, REG_SAVE3); \
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arm_block_memory_writeback_##access_type(writeback_type); \
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generate_and_imm(s0, ~0x03); \
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\
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for(i = 0; i < 16; i++) \
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{ \
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if((reg_list >> i) & 0x01) \
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{ \
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cycle_count++; \
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generate_add_reg_reg_imm(a0, s0, offset) \
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generate_load_reg(a0, REG_SAVE3); \
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generate_add_imm(a0, offset) \
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if(reg_list & ~((2 << i) - 1)) \
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{ \
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arm_block_memory_##access_type(); \
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@ -1595,11 +1597,11 @@ u32 function_cc execute_store_cpsr_body(u32 _cpsr)
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generate_load_reg(a0, rn); \
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generate_load_pc(a1, pc); \
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generate_function_call(execute_load_##type); \
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generate_mov(s0, rv); \
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generate_mov(a2, rv); \
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generate_load_reg(a0, rn); \
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generate_load_reg(a1, rm); \
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generate_store_reg(a2, rd); \
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generate_function_call(execute_store_##type); \
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generate_store_reg(s0, rd); \
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} \
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#define thumb_rn_op_reg(_rn) \
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@ -1823,34 +1825,33 @@ u32 function_cc execute_store_cpsr_body(u32 _cpsr)
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} \
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#define thumb_block_address_preadjust_up() \
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generate_add_imm(s0, (bit_count[reg_list] * 4)) \
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generate_add_imm(a0, (bit_count[reg_list] * 4)) \
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#define thumb_block_address_preadjust_down() \
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generate_sub_imm(s0, (bit_count[reg_list] * 4)) \
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generate_sub_imm(a0, (bit_count[reg_list] * 4)) \
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#define thumb_block_address_preadjust_push_lr() \
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generate_sub_imm(s0, ((bit_count[reg_list] + 1) * 4)) \
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generate_sub_imm(a0, ((bit_count[reg_list] + 1) * 4)) \
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#define thumb_block_address_preadjust_no() \
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#define thumb_block_address_postadjust_no(base_reg) \
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generate_store_reg(s0, base_reg) \
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generate_store_reg(a0, base_reg) \
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#define thumb_block_address_postadjust_up(base_reg) \
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generate_add_reg_reg_imm(a0, s0, (bit_count[reg_list] * 4)); \
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generate_add_imm(a0, (bit_count[reg_list] * 4)); \
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generate_store_reg(a0, base_reg) \
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#define thumb_block_address_postadjust_down(base_reg) \
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generate_mov(a0, s0); \
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generate_sub_imm(a0, (bit_count[reg_list] * 4)); \
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generate_store_reg(a0, base_reg) \
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#define thumb_block_address_postadjust_pop_pc(base_reg) \
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generate_add_reg_reg_imm(a0, s0, ((bit_count[reg_list] + 1) * 4)); \
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generate_add_imm(a0, ((bit_count[reg_list] + 1) * 4)); \
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generate_store_reg(a0, base_reg) \
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#define thumb_block_address_postadjust_push_lr(base_reg) \
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generate_store_reg(s0, base_reg) \
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generate_store_reg(a0, base_reg) \
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#define thumb_block_memory_extra_no() \
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@ -1859,7 +1860,8 @@ u32 function_cc execute_store_cpsr_body(u32 _cpsr)
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#define thumb_block_memory_extra_down() \
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#define thumb_block_memory_extra_pop_pc() \
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generate_add_reg_reg_imm(a0, s0, (bit_count[reg_list] * 4)); \
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generate_load_reg(a0, REG_SAVE3); \
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generate_add_imm(a0, (bit_count[reg_list] * 4)); \
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generate_load_pc(a1, pc); \
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generate_function_call(execute_load_u32); \
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generate_store_reg(rv, REG_PC); \
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@ -1867,7 +1869,8 @@ u32 function_cc execute_store_cpsr_body(u32 _cpsr)
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generate_indirect_branch_cycle_update(thumb) \
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#define thumb_block_memory_extra_push_lr(base_reg) \
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generate_add_reg_reg_imm(a0, s0, (bit_count[reg_list] * 4)); \
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generate_load_reg(a0, REG_SAVE3); \
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generate_add_imm(a0, (bit_count[reg_list] * 4)); \
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generate_load_reg(a1, REG_LR); \
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generate_function_call(execute_store_aligned_u32) \
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@ -1909,9 +1912,10 @@ u32 function_cc execute_store_cpsr_body(u32 _cpsr)
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u32 i; \
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u32 offset = 0; \
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\
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generate_load_reg(s0, base_reg); \
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generate_and_imm(s0, ~0x03); \
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generate_load_reg(a0, base_reg); \
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generate_and_imm(a0, ~0x03); \
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thumb_block_address_preadjust_##pre_op(); \
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generate_store_reg(a0, REG_SAVE3); \
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thumb_block_address_postadjust_##post_op(base_reg); \
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\
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for(i = 0; i < 8; i++) \
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@ -1919,7 +1923,8 @@ u32 function_cc execute_store_cpsr_body(u32 _cpsr)
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if((reg_list >> i) & 0x01) \
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{ \
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cycle_count++; \
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generate_add_reg_reg_imm(a0, s0, offset) \
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generate_load_reg(a0, REG_SAVE3); \
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generate_add_imm(a0, offset) \
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if(reg_list & ~((2 << i) - 1)) \
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{ \
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thumb_block_memory_##access_type(); \
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