Commit Graph

56 Commits

Author SHA1 Message Date
andymcca 2fcbdc1d17
MODE_UNDEFINED is 0x1B (not 0x1C) (#184)
In the cpu_modes array, MODE_UNDEFINED is at position 0x1C, but this mode value is actually 0x1B.
2023-01-21 21:44:23 +01:00
David Guillen Fandos 4f3c9a5e58 [all] Fix CPSR and CPU modes
gpsp doesn't differentiate between USER and SYSTEM mode, most likely
cause it is not that important for most games. This implements the modes
correctly and adds checks for privileged operations. Still some
bugs/hacks but it mostly fixes CPSR/SPSR reads/writes.

To implement PSR writes we are using a more refined masks and force mode
bit num. 4 to always be one. Reserved bits are forced to zero (this
needs to be validated on a real device).
2023-01-11 21:26:32 +01:00
David Guillen Fandos b552d5eb7e Improve open bus reads on ARM/MIPS 2023-01-05 21:29:20 +01:00
David Guillen Fandos 3a6ca8d941 Better cycle accounting, taking remainders partially into account 2021-12-21 19:59:33 +01:00
David Guillen Fandos c30f910fe8 [interpreter] Fix many flag related bugs including Op2 C flag
This fixes a few games and GBA-V too. C flag was neglected on Op2
immediate. Many add/adc related ops were broken due to carry in.
2021-12-14 00:46:37 +01:00
David Guillen Fandos 92180d5d7e Minor unused stuff cleanup 2021-11-06 21:49:08 +01:00
David Guillen Fandos 5c1467cb63 [ARM] Remove cross calls between cache and text (far calls)
This is to allow cache to be mapped far from the regular .text section
2021-10-29 22:34:29 +02:00
David Guillen Fandos 3cab8596b8 Fix SWI handling (disable IRQs)
This introduced a potential race condition between the start of a SWI
and the BIOS handling the exception by returning to system mode. During
this ~10 instruction window, having an IRQ that issues a SWI causes bad
behaviour that results in crashes or other weirdness.
Fixes a couple of games and potentially many weird and obscure bugs here
and there (hard to reproduce sometimes).
2021-09-17 22:22:01 +02:00
David Guillen Fandos ed89923fda Minor mem fixes around mirrors and u8/u16 accesses
Improve the open bus access a bit too.
2021-09-17 21:30:33 +02:00
David Guillen Fandos 8fabfaf2a8 Fix shift by register in interpreter
Only the LSB byte is actually used.
2021-09-17 20:17:51 +02:00
David Guillen Fandos 8207775256 Fix out of bounds read bug on open bus read
This bug doesn't affect many games but makes sanitizers unhappy.
Also fix some minor FIFO clear bug
2021-08-24 19:55:37 +02:00
David Guillen Fandos 7068cbc95b New savestate implementation
This uses BSON as savestate format, to allow external tools to parse it
(so that we can add proper test of the states). The BSON is not 100%
correct according to spec (no ordered keys) but can be parsed by most
libraries.

This fixes also a bug in the savestate palette color recalculation that
was wrongly overwritting the original palette (which could cause some
problems on some games).

Also fixes some potential issues by serializing some more stuff and
cleans up unused stuff.

Testing shows that states look good and there's only minor differences
in audio ticks, related to buffer sizes (since buffer flushes are
de-synced from video frames due to different frequency).
2021-08-24 17:15:27 +02:00
David Guillen Fandos 1e976fb312 Remove unused stuff and fix const variables
Trying to figure out what needs to be part of a savestate :)
2021-08-24 10:57:30 +02:00
David Guillen Fandos 745b2ece2c Fix inifinite loop in the interpreter, fixes ~6 games
Seems that, on IRQ, it is assumed that the PC will change (which happens
most of the time). However if the IRQ is masked it resumes execution.
On masked DMA IRQ the interpreter jumps to alert without incrementing
the instruction pointer (right after).
2021-08-15 23:02:12 +02:00
David Guillen Fandos 5be5015338 Rearrange register layout and exclude useless regs from savestat
This changes the savestate format once again.
2021-08-15 21:07:20 +02:00
David Guillen Fandos ce14e2585b Fix and reenable Android arm 32 bit builds
Removed the last bits of text relocations by moving all relevant RAMs to
the stub reachable area. This should be as fast or even faster than
previous code.
2021-07-31 17:45:46 +02:00
David Guillen Fandos ab7d9bb161 Move membuffers close to dynarec area to fix x86 relocs
This essentially makes it easier to get a relocation-free text area for
x86 so that Android loaders are happy.
2021-07-28 19:12:43 +02:00
David Guillen Fandos 84cd7b2934 Rewrite ROM buffer allocation
This improves the existing on-demand ROM paging and also breaks down ROM
buffers into 1MB blocks for platforms with memory fragmentation issues.

Fixed some potential RTC reg issue in said platforms too.
Fixed page pinning on interpreter (would crash due to LRU evictions).
2021-07-14 01:20:30 +02:00
David Guillen Fandos c9421e6929 Some small cleanup to make the code more C++ conformant 2021-07-11 13:35:21 +02:00
David Guillen Fandos 836e51b694 Fix some UB behaviour 2021-07-01 12:06:57 +02:00
David Guillen Fandos 8dbf5f6c17 Enable big-endian devices: gc/wii
This patch adds big-endian compatibility in gpsp (in general but only
for the interpreter). There's no performance hit for little-endian
platforms (should be a no-op) and only add a small overhead in memory
accesses for big-endian platforms.

Most memory accesses are wrapped with a byteswap instruction and I/O reg
accesses are also rewired for proper access (using macros). Video
rendering has been fixed to also do byteswaps but there's a couple of
games and rendering modes that still seem broken (but they amount to
less than 20 games in my tests with 1K ROMs).

This also adds build rules and CI for NGC/WII/WIIU (untested)
2021-06-27 01:16:28 +02:00
David Guillen Fandos 7a642069e3 Cleanup unused stuff 2021-06-09 18:10:26 +02:00
David Guillen Fandos 37430f22c5 Small optimization (~2-4%) and whitespace cleanup!
Cleans up a ton of whitespace in cpu.c (like 100KB!) and improves
readability of some massive decode statements.

Added an optimization for PC-relative loads (pool load) in ROM (since
it's read only and cannot possibily change) that directly emits an
immediate load. This is way faster, specially in MIPS/x86, ARM can be
even faster if we rewrite the immediate load macros to also use a pool.
2021-05-07 20:41:54 +02:00
David Guillen Fandos 7877a8888b Fix aligned32 reads in interpreter mode
An address check was missing to read aligned 32 (stm/ldm) data from
high mem areas (0xX0000000). This fixes SM4 EU that for some reason has
some weird memory access (perhaps a bug?)
2021-05-05 21:33:48 +02:00
David Guillen Fandos 4fd456e158 Adding Code Breaker cheat support
This works on both interpreter and dynarec.
Tested in MIPS, ARM and x86, still needs some more testing, some edge
cases can be buggy.
2021-05-05 21:15:27 +02:00
David Guillen Fandos 7ea6c5e247 Move OAM RAM to stubs also
Makes accesses more efficient for MIPS. Make accesses also fast for palette
reads.
2021-03-26 23:13:26 +01:00
David Guillen Fandos 11ec213c99 Make ewram memory lineal
This saves a few cycles in MIPS and simplifies a bit the core.
Removed the write map, only affects interpreter performance very
minimally. Rewired ARM and x86 handlers to support direct access to
I/EWRAM (and VRAM on ARM) to compensate. Overall performance is slightly
better but code is cleaner and allows for further improvements in the
dynarecs.
2021-03-23 19:09:56 +01:00
David Guillen Fandos f6f3a91039 Adding Normmatt's BIOS as a built-in BIOS
Add options to select whether to boot from BIOS (default is no, as it is
now) and whether to use the original bios or the builtin one (default is
auto, which tries to use the official but falls back to the builtin if
not found).
2021-03-22 21:45:52 +01:00
David Guillen Fandos fb7ca09b01 Remove BIOS reserved translation area
This is not really necessary since it can share area with ROM.
Performance impact should be very minimal (haven't noticed it myself)
and could be compensated (even by a positive offset) if we bump the ROM
cache area size.
Tested with several dynarecs.
2021-03-17 18:33:02 +01:00
David Guillen Fandos 46cad2958a Move a few more registers to context
This gets rid of some more absolute addrs in the MIPS dynarec.
Tested on several platforms, we should be good.
2021-03-16 01:02:10 +01:00
David Guillen Fandos c86b9064df Move palettes around to simplify MIPS dynarec
Will move also OAM structures to gain a few cycles per load/store.
Loads can also be optimized for an extra instruction per access.
2021-03-15 02:25:02 +01:00
David Guillen Fandos 56dc6ecb70 Remove libco
This removes libco and all the usages of it (+pthreads).
Rewired all dynarecs and interpreter to return after every frame so that
libretro can process events. This required to make dynarec re-entrant.

Dynarecs were updated to check for new frame on every update (IRQ, cycle
exhaustion, I/O write, etc). The performance impact of doing so should
be minimal (and definitely outweight the libco gains). While at it,
fixed small issues to get a bit more perf: arm dynarec was not idling
correctly, mips was using stack when not needed, etc.

Tested on PSP (mips), OGA (armv7), Linux (x86 and interpreter). Not
tested on Android though.
2021-03-08 18:44:03 +01:00
twinaphex 4036107852 Prevent bunch of warnings 2015-07-26 04:44:17 +02:00
twinaphex cf973d0c5f Rename cpu_orig.c to cpu.c 2014-12-14 02:51:43 +01:00
twinaphex cefd5b63ee Remove a lot of the GNU case range extensions instances 2014-12-13 04:50:48 +01:00
twinaphex 72573712d3 CPU interpreter - group more case ranges together 2014-12-12 16:52:23 +01:00
twinaphex 701e2bbf50 CPU interpreter - group THUMB cases 0x38 to 0x3F (SUB) together 2014-12-12 06:48:20 +01:00
twinaphex 4a6d527b1c Use thumb_opcode_val & 0x7 instead 2014-12-12 06:45:20 +01:00
twinaphex c1677498a5 CPU interpreter - group THUMB case range 0x30 to 0x37 (ADD) together 2014-12-12 06:42:59 +01:00
twinaphex 4a860b662e CPU interpreter - group THUMB cases 0x28 to 0x2F together 2014-12-12 06:35:17 +01:00
twinaphex ade2bed514 CPU interpreter - group Thumb opcode case ranges 0x20 - 0x27 together 2014-12-12 06:31:16 +01:00
twinaphex f9079ff9fb execute_arm_instruction and execute_thumb_instruction - throw them
straight into execute_arm/execute_thumb functions
2014-12-12 06:12:00 +01:00
twinaphex 51d78afa09 Add HAVE_DYNAREC ifdef 2014-12-10 17:06:09 +01:00
twinaphex 512f7f5b27 Code nits - get rid of '== NULL' / '!= NULL' 2014-12-10 16:40:43 +01:00
twinaphex 7a0b0cba45 Style nits 2014-12-10 15:47:19 +01:00
aliaspider a926a68eb3 cleanups 2014-12-10 12:53:26 +01:00
aliaspider ad485d434a implement retro_serialize/unserialize 2014-12-10 11:06:17 +01:00
twinaphex ce374b460b Remove SDL code in cpu.c 2014-12-10 01:30:47 +01:00
twinaphex fe19474dca Add macro parameter 'opcode' to some macros 2014-12-10 01:17:37 +01:00
twinaphex 5c949f38e4 Assume PC_BUILD 2014-12-09 17:18:45 +01:00