Move OAM RAM to stubs also
Makes accesses more efficient for MIPS. Make accesses also fast for palette reads.
This commit is contained in:
David Guillen Fandos
parent
a494a3f00e
commit
7ea6c5e247
9
Makefile
9
Makefile
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@ -362,6 +362,15 @@ else ifneq (,$(findstring armv,$(platform)))
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endif
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LDFLAGS := -Wl,--no-undefined
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# MIPS
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else ifeq ($(platform), mips32)
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TARGET := $(TARGET_NAME)_libretro.so
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SHARED := -shared -nostdlib -Wl,--version-script=link.T
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fpic := -fPIC -DPIC
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CFLAGS += -fomit-frame-pointer -ffast-math -march=mips32 -mtune=mips32r2 -mhard-float
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HAVE_DYNAREC := 1
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CPU_ARCH := mips
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# emscripten
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else ifeq ($(platform), emscripten)
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TARGET := $(TARGET_NAME)_libretro_$(platform).bc
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@ -820,6 +820,8 @@ defsymbl(palette_ram)
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.space 0x400
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defsymbl(palette_ram_converted)
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.space 0x400
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defsymbl(oam_ram)
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.space 0x400
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defsymbl(spsr)
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.space 24
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defsymbl(reg_mode)
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1
cpu.c
1
cpu.c
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@ -1630,6 +1630,7 @@ void raise_interrupt(irq_type irq_raised)
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#ifndef HAVE_DYNAREC
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u8 *memory_map_read [8 * 1024];
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u16 oam_ram[512];
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u16 palette_ram[512];
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u16 palette_ram_converted[512];
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#endif
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@ -305,7 +305,6 @@ u32 gamepak_waitstate_sequential[2][3][3] =
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}
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};
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u16 oam_ram[512];
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u16 io_registers[1024 * 16];
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u8 ewram[1024 * 256 * 2];
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u8 iwram[1024 * 32 * 2];
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@ -2630,6 +2630,7 @@ typedef struct {
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bool check_smc; // Whether the memory can contain code
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bool bus16; // Whether it can only be accessed at 16bit
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u32 baseptr; // Memory base address.
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u32 baseoff; // Offset from base_reg
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} t_stub_meminfo;
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// Generates the stub to access memory for a given region, access type,
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@ -2738,7 +2739,11 @@ static void emit_pmemld_stub(
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} else {
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// Generate upper bits of the addr and do addr mirroring
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// (The address hi16 is rounded up since load uses signed offset)
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mips_emit_lui(reg_rv, ((base_addr + 0x8000) >> 16));
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if (!meminfo->baseoff) {
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mips_emit_lui(reg_rv, ((base_addr + 0x8000) >> 16));
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} else {
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base_addr = meminfo->baseoff;
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}
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if (region == 2) {
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// Can't do EWRAM with an `andi` instruction (18 bits mask)
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@ -2761,8 +2766,9 @@ static void emit_pmemld_stub(
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mips_emit_addu(reg_rv, reg_rv, reg_a0); // addr = base + adjusted offset
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} else {
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// Generate regular (<=32KB) mirroring
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mips_emit_andi(reg_a0, reg_a0, memmask); // Clear upper bits (mirroring)
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mips_emit_addu(reg_rv, reg_rv, reg_a0); // Adds to base addr
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mips_reg_number breg = (meminfo->baseoff ? reg_base : reg_rv);
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mips_emit_andi(reg_temp, reg_a0, memmask); // Clear upper bits (mirroring)
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mips_emit_addu(reg_rv, breg, reg_temp); // Adds to base addr
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}
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}
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@ -3154,7 +3160,7 @@ static void emit_phand(
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mips_emit_ins(reg_temp, reg_a0, 6, size); // Alignment bits (1 or 2, to bits 6 (and 7)
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}
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unsigned tbloff = 256 + 2048 + 220 + 4 * toff; // Skip regs and palettes
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unsigned tbloff = 256 + 3*1024 + 220 + 4 * toff; // Skip regs and RAMs
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mips_emit_addu(reg_rv, reg_temp, reg_base); // Add to the base_reg the table offset
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mips_emit_lw(reg_rv, reg_rv, tbloff); // Read addr from table
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mips_emit_sll(reg_temp, reg_rv, 4); // 26 bit immediate to the MSB
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@ -3229,21 +3235,21 @@ void init_emitter() {
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// Generate memory handlers
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const t_stub_meminfo ldinfo [] = {
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{ emit_pmemld_stub, 0, 0x4000, false, false, (u32)bios_rom },
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{ emit_pmemld_stub, 0, 0x4000, false, false, (u32)bios_rom, 0},
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// 1 Open load / Ignore store
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{ emit_pmemld_stub, 2, 0x8000, true, false, (u32)ewram }, // memsize wrong on purpose
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{ emit_pmemld_stub, 3, 0x8000, true, false, (u32)&iwram[0x8000] },
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{ emit_pmemld_stub, 4, 0x400, false, false, (u32)io_registers },
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{ emit_pmemld_stub, 5, 0x400, false, true, (u32)palette_ram },
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{ emit_pmemld_stub, 6, 0x0, false, true, (u32)vram }, // same, vram is a special case
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{ emit_pmemld_stub, 7, 0x400, false, true, (u32)oam_ram },
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{ emit_pmemld_stub, 8, 0x8000, false, false, 0 },
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{ emit_pmemld_stub, 9, 0x8000, false, false, 0 },
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{ emit_pmemld_stub, 10, 0x8000, false, false, 0 },
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{ emit_pmemld_stub, 11, 0x8000, false, false, 0 },
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{ emit_pmemld_stub, 12, 0x8000, false, false, 0 },
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{ emit_pmemld_stub, 2, 0x8000, true, false, (u32)ewram, 0 }, // memsize wrong on purpose
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{ emit_pmemld_stub, 3, 0x8000, true, false, (u32)&iwram[0x8000], 0 },
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{ emit_pmemld_stub, 4, 0x400, false, false, (u32)io_registers, 0 },
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{ emit_pmemld_stub, 5, 0x400, false, true, (u32)palette_ram, 0x100 },
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{ emit_pmemld_stub, 6, 0x0, false, true, (u32)vram, 0 }, // same, vram is a special case
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{ emit_pmemld_stub, 7, 0x400, false, true, (u32)oam_ram, 0x900 },
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{ emit_pmemld_stub, 8, 0x8000, false, false, 0, 0 },
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{ emit_pmemld_stub, 9, 0x8000, false, false, 0, 0 },
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{ emit_pmemld_stub, 10, 0x8000, false, false, 0, 0 },
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{ emit_pmemld_stub, 11, 0x8000, false, false, 0, 0 },
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{ emit_pmemld_stub, 12, 0x8000, false, false, 0, 0 },
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// 13 is EEPROM mapped already (a bit special)
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{ emit_pmemld_stub, 14, 0, false, false, 0 }, // Mapped via function call
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{ emit_pmemld_stub, 14, 0, false, false, 0, 0 }, // Mapped via function call
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// 15 Open load / Ignore store
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};
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@ -3267,12 +3273,12 @@ void init_emitter() {
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}
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const t_stub_meminfo stinfo [] = {
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{ emit_pmemst_stub, 2, 0x8000, true, false, (u32)ewram },
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{ emit_pmemst_stub, 3, 0x8000, true, false, (u32)&iwram[0x8000] },
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{ emit_pmemst_stub, 2, 0x8000, true, false, (u32)ewram, 0 },
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{ emit_pmemst_stub, 3, 0x8000, true, false, (u32)&iwram[0x8000], 0 },
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// I/O is special and mapped with a function call
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{ emit_palette_hdl, 5, 0x400, false, true, (u32)palette_ram },
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{ emit_pmemst_stub, 6, 0x0, false, true, (u32)vram }, // same, vram is a special case
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{ emit_pmemst_stub, 7, 0x400, false, true, (u32)oam_ram },
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{ emit_palette_hdl, 5, 0x400, false, true, (u32)palette_ram, 0x100 },
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{ emit_pmemst_stub, 6, 0x0, false, true, (u32)vram, 0 }, // same, vram is a special case
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{ emit_pmemst_stub, 7, 0x400, false, true, (u32)oam_ram, 0x900 },
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};
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// Store only for "regular"-ish mem regions
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@ -40,6 +40,7 @@
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.global reg_check
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.global palette_ram
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.global palette_ram_converted
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.global oam_ram
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.global init_emitter
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.global mips_lookup_pc
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.global smc_write
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@ -120,11 +121,12 @@
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.equ OAM_UPDATED, (33 * 4)
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.equ GP_SAVE, (34 * 4)
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.equ SPSR_BASE, (0x900)
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.equ REGMODE_BASE, (0x900 + 24)
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.equ SPSR_BASE, (0x100 + 0x400 * 3)
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.equ REGMODE_BASE, (SPSR_BASE + 24)
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.equ SUPERVISOR_SPSR, (3 * 4 + SPSR_BASE)
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.equ SUPERVISOR_LR, ((3 * (7 * 4)) + (6 * 4) + REGMODE_BASE)
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.equ FNPTRS_BASE, (0x900 + 220 + 960)
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.equ FNPTRS_MEMOPS, (REGMODE_BASE + 196)
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.equ FNPTRS_BASE, (FNPTRS_MEMOPS + 960)
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.set noat
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.set noreorder
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@ -625,6 +627,8 @@ palette_ram:
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.space 0x400
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palette_ram_converted:
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.space 0x400
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oam_ram:
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.space 0x400
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spsr:
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.space 24 # u32[6]
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reg_mode:
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@ -538,6 +538,8 @@ defsymbl(palette_ram)
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.space 0x400
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defsymbl(palette_ram_converted)
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.space 0x400
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defsymbl(oam_ram)
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.space 0x400
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defsymbl(spsr)
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.space 24
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defsymbl(reg_mode)
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