[interpreter] Fix many flag related bugs including Op2 C flag
This fixes a few games and GBA-V too. C flag was neglected on Op2 immediate. Many add/adc related ops were broken due to carry in.
This commit is contained in:
David Guillen Fandos
parent
9b25f26ed8
commit
c30f910fe8
101
cpu.c
101
cpu.c
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@ -173,9 +173,10 @@ void print_register_usage(void)
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u32 imm; \
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u32 rn = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 imm_ror = ((opcode >> 8) & 0xF) << 1; \
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(void)rd; \
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(void)rn; \
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ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2); \
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ror(imm, opcode & 0xFF, imm_ror); \
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using_register(arm, rd, op_dest); \
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using_register(arm, rn, op_src) \
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@ -282,7 +283,7 @@ void print_register_usage(void)
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u32 rd = opcode & 0x07; \
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using_register(thumb, rd, op_dest); \
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using_register(thumb, rn, op_src); \
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using_register(thumb, rn, op_src) \
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using_register(thumb, rs, op_src) \
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#define thumb_decode_add_sub_imm() \
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u32 imm = (opcode >> 6) & 0x07; \
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@ -358,18 +359,15 @@ void print_register_usage(void)
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#define calculate_n_flag(dest) \
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n_flag = ((signed)dest < 0) \
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#define calculate_c_flag_sub(dest, src_a, src_b) \
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c_flag = ((unsigned)src_b <= (unsigned)src_a) \
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#define calculate_c_flag_sub(dest, src_a, src_b, carry) \
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c_flag = (carry) ? ((unsigned)src_b <= (unsigned)src_a) : \
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((unsigned)src_b < (unsigned)src_a); \
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#define calculate_v_flag_sub(dest, src_a, src_b) \
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v_flag = ((signed)src_b > (signed)src_a) != ((signed)dest < 0) \
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#define calculate_c_flag_add(dest, src_a, src_b) \
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c_flag = ((unsigned)dest < (unsigned)src_a) \
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v_flag = (((src_a ^ src_b) & (~src_b ^ dest)) >> 31)
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#define calculate_v_flag_add(dest, src_a, src_b) \
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v_flag = ((signed)dest < (signed)src_a) != ((signed)src_b < 0) \
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v_flag = ((~((src_a) ^ (src_b)) & ((src_a) ^ (dest))) >> 31)
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#define calculate_reg_sh() \
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u32 reg_sh = 0; \
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@ -661,13 +659,12 @@ void print_register_usage(void)
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#define calculate_flags_add(dest, src_a, src_b) \
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calculate_z_flag(dest); \
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calculate_n_flag(dest); \
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calculate_c_flag_add(dest, src_a, src_b); \
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calculate_v_flag_add(dest, src_a, src_b) \
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#define calculate_flags_sub(dest, src_a, src_b) \
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#define calculate_flags_sub(dest, src_a, src_b, carry) \
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calculate_z_flag(dest); \
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calculate_n_flag(dest); \
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calculate_c_flag_sub(dest, src_a, src_b); \
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calculate_c_flag_sub(dest, src_a, src_b, carry); \
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calculate_v_flag_sub(dest, src_a, src_b) \
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#define calculate_flags_logic(dest) \
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@ -756,6 +753,8 @@ void print_register_usage(void)
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#define arm_data_proc_flags_imm() \
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arm_decode_data_proc_imm(opcode) \
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if(imm_ror) \
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c_flag = (imm >> 31); /* imm is rotated already! */ \
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#define arm_data_proc_imm() \
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arm_decode_data_proc_imm(opcode) \
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@ -791,25 +790,30 @@ void print_register_usage(void)
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arm_spsr_restore(); \
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} \
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#define arm_data_proc_add_flags(src_a, src_b, type) \
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#define arm_data_proc_add_flags(src_a, src_b, src_c, type) \
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{ \
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u32 _sc = src_c; \
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arm_pc_offset(8); \
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arm_data_proc_##type(); \
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flags_vars(src_a, src_b); \
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dest = _sa + _sb; \
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c_flag = (dest < _sb); \
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dest += _sc; \
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c_flag |= (dest < _sc); \
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calculate_flags_add(dest, _sa, _sb); \
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arm_pc_offset(-4); \
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reg[rd] = dest; \
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arm_spsr_restore(); \
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}
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#define arm_data_proc_sub_flags(src_a, src_b, type) \
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#define arm_data_proc_sub_flags(src_a, src_b, src_c, type) \
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{ \
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u32 _sc = src_c; \
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arm_pc_offset(8); \
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arm_data_proc_##type(); \
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flags_vars(src_a, src_b); \
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dest = _sa - _sb; \
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calculate_flags_sub(dest, _sa, _sb); \
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dest = _sa + (~(_sb)) + _sc; \
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calculate_flags_sub(dest, _sa, _sb, _sc); \
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arm_pc_offset(-4); \
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reg[rd] = dest; \
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arm_spsr_restore(); \
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@ -830,6 +834,7 @@ void print_register_usage(void)
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arm_data_proc_##type(); \
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flags_vars(src_a, src_b); \
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dest = _sa + _sb; \
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c_flag = (dest < _sb); \
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calculate_flags_add(dest, _sa, _sb); \
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arm_pc_offset(-4); \
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} \
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@ -840,7 +845,7 @@ void print_register_usage(void)
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arm_data_proc_##type(); \
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flags_vars(src_a, src_b); \
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dest = _sa - _sb; \
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calculate_flags_sub(dest, _sa, _sb); \
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calculate_flags_sub(dest, _sa, _sb, 1); \
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arm_pc_offset(-4); \
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} \
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@ -1202,12 +1207,16 @@ const u32 psr_masks[16] =
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// Types: add_sub, add_sub_imm, alu_op, imm
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// Affects N/Z/C/V flags
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#define thumb_add(type, dest_reg, src_a, src_b) \
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#define thumb_add(type, dest_reg, src_a, src_b, src_c) \
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{ \
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const u32 _sc = src_c; \
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thumb_decode_##type(); \
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const u32 _sa = src_a; \
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const u32 _sb = src_b; \
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u32 dest = _sa + _sb; \
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c_flag = (dest < _sb); \
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dest += _sc; \
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c_flag |= (dest < _sc); \
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calculate_flags_add(dest, _sa, _sb); \
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reg[dest_reg] = dest; \
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thumb_pc_offset(2); \
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@ -1221,13 +1230,14 @@ const u32 psr_masks[16] =
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thumb_pc_offset(2); \
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} \
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#define thumb_sub(type, dest_reg, src_a, src_b) \
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#define thumb_sub(type, dest_reg, src_a, src_b, src_c) \
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{ \
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thumb_decode_##type(); \
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const u32 _sa = src_a; \
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const u32 _sb = src_b; \
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u32 dest = _sa - _sb; \
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calculate_flags_sub(dest, _sa, _sb); \
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const u32 _sc = src_c; \
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u32 dest = _sa + (~_sb) + _sc; \
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calculate_flags_sub(dest, _sa, _sb, _sc); \
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reg[dest_reg] = dest; \
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thumb_pc_offset(2); \
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} \
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@ -1378,6 +1388,7 @@ const u32 psr_masks[16] =
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const u32 _sa = src_a; \
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const u32 _sb = src_b; \
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u32 dest = _sa + _sb; \
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c_flag = (dest < _sb); \
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calculate_flags_add(dest, src_a, src_b); \
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thumb_pc_offset(2); \
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} \
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@ -1388,7 +1399,7 @@ const u32 psr_masks[16] =
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const u32 _sa = src_a; \
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const u32 _sb = src_b; \
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u32 dest = _sa - _sb; \
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calculate_flags_sub(dest, src_a, src_b); \
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calculate_flags_sub(dest, src_a, src_b, 1); \
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thumb_pc_offset(2); \
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} \
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@ -1896,7 +1907,7 @@ arm_loop:
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else
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{
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/* SUBS rd, rn, reg_op */
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arm_data_proc_sub_flags(reg[rn], reg_sh, reg);
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arm_data_proc_sub_flags(reg[rn], reg_sh, 1, reg);
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}
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break;
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@ -1937,7 +1948,7 @@ arm_loop:
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else
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{
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/* RSBS rd, rn, reg_op */
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arm_data_proc_sub_flags(reg_sh, reg[rn], reg);
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arm_data_proc_sub_flags(reg_sh, reg[rn], 1, reg);
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}
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break;
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@ -1991,7 +2002,7 @@ arm_loop:
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else
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{
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/* ADDS rd, rn, reg_op */
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arm_data_proc_add_flags(reg[rn], reg_sh, reg);
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arm_data_proc_add_flags(reg[rn], reg_sh, 0, reg);
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}
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break;
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@ -2045,7 +2056,7 @@ arm_loop:
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else
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{
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/* ADCS rd, rn, reg_op */
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arm_data_proc_add_flags(reg[rn], reg_sh + c_flag, reg);
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arm_data_proc_add_flags(reg[rn], reg_sh, c_flag, reg);
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}
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break;
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@ -2099,7 +2110,7 @@ arm_loop:
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else
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{
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/* SBCS rd, rn, reg_op */
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arm_data_proc_sub_flags(reg[rn], (reg_sh + (c_flag ^ 1)), reg);
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arm_data_proc_sub_flags(reg[rn], reg_sh, c_flag, reg);
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}
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break;
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@ -2153,7 +2164,7 @@ arm_loop:
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else
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{
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/* RSCS rd, rn, reg_op */
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arm_data_proc_sub_flags((reg_sh + c_flag - 1), reg[rn], reg);
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arm_data_proc_sub_flags(reg_sh, reg[rn], c_flag, reg);
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}
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break;
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@ -2548,7 +2559,7 @@ arm_loop:
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case 0x25:
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/* SUBS rd, rn, imm */
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arm_data_proc_sub_flags(reg[rn], imm, imm);
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arm_data_proc_sub_flags(reg[rn], imm, 1, imm);
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break;
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case 0x26:
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@ -2558,7 +2569,7 @@ arm_loop:
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case 0x27:
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/* RSBS rd, rn, imm */
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arm_data_proc_sub_flags(imm, reg[rn], imm);
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arm_data_proc_sub_flags(imm, reg[rn], 1, imm);
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break;
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case 0x28:
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@ -2568,7 +2579,7 @@ arm_loop:
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case 0x29:
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/* ADDS rd, rn, imm */
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arm_data_proc_add_flags(reg[rn], imm, imm);
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arm_data_proc_add_flags(reg[rn], imm, 0, imm);
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break;
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case 0x2A:
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@ -2578,7 +2589,7 @@ arm_loop:
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case 0x2B:
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/* ADCS rd, rn, imm */
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arm_data_proc_add_flags(reg[rn] + imm, c_flag, imm);
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arm_data_proc_add_flags(reg[rn], imm, c_flag, imm);
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break;
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case 0x2C:
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@ -2588,7 +2599,7 @@ arm_loop:
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case 0x2D:
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/* SBCS rd, rn, imm */
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arm_data_proc_sub_flags(reg[rn], (imm + (c_flag ^ 1)), imm);
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arm_data_proc_sub_flags(reg[rn], imm, c_flag, imm);
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break;
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case 0x2E:
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@ -2598,7 +2609,7 @@ arm_loop:
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case 0x2F:
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/* RSCS rd, rn, imm */
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arm_data_proc_sub_flags((imm + c_flag - 1), reg[rn], imm);
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arm_data_proc_sub_flags(imm, reg[rn], c_flag, imm);
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break;
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case 0x30:
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@ -3258,25 +3269,25 @@ thumb_loop:
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case 0x18:
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case 0x19:
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/* ADD rd, rs, rn */
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thumb_add(add_sub, rd, reg[rs], reg[rn]);
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thumb_add(add_sub, rd, reg[rs], reg[rn], 0);
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break;
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case 0x1A:
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case 0x1B:
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/* SUB rd, rs, rn */
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thumb_sub(add_sub, rd, reg[rs], reg[rn]);
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thumb_sub(add_sub, rd, reg[rs], reg[rn], 1);
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break;
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case 0x1C:
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case 0x1D:
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/* ADD rd, rs, imm */
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thumb_add(add_sub_imm, rd, reg[rs], imm);
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thumb_add(add_sub_imm, rd, reg[rs], imm, 0);
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break;
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case 0x1E:
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case 0x1F:
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/* SUB rd, rs, imm */
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thumb_sub(add_sub_imm, rd, reg[rs], imm);
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thumb_sub(add_sub_imm, rd, reg[rs], imm, 1);
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break;
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case 0x20 ... 0x27:
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@ -3291,12 +3302,12 @@ thumb_loop:
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case 0x30 ... 0x37:
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/* ADD r0..7, imm */
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thumb_add(imm, ((opcode >> 8) & 7), reg[(opcode >> 8) & 7], imm);
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thumb_add(imm, ((opcode >> 8) & 7), reg[(opcode >> 8) & 7], imm, 0);
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break;
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case 0x38 ... 0x3F:
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/* SUB r0..7, imm */
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thumb_sub(imm, ((opcode >> 8) & 7), reg[(opcode >> 8) & 7], imm);
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thumb_sub(imm, ((opcode >> 8) & 7), reg[(opcode >> 8) & 7], imm, 1);
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break;
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case 0x40:
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@ -3334,12 +3345,12 @@ thumb_loop:
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case 0x01:
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/* ADC rd, rs */
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thumb_add(alu_op, rd, reg[rd] + reg[rs], c_flag);
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thumb_add(alu_op, rd, reg[rd], reg[rs], c_flag);
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break;
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case 0x02:
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/* SBC rd, rs */
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thumb_sub(alu_op, rd, reg[rd] - reg[rs], (c_flag ^ 1));
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thumb_sub(alu_op, rd, reg[rd], reg[rs], c_flag);
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break;
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case 0x03:
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@ -3359,7 +3370,7 @@ thumb_loop:
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case 0x01:
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/* NEG rd, rs */
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thumb_sub(alu_op, rd, 0, reg[rs]);
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thumb_sub(alu_op, rd, 0, reg[rs], 1);
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break;
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case 0x02:
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@ -3413,7 +3424,7 @@ thumb_loop:
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u32 _sb = reg[rs];
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u32 dest = _sa - _sb;
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thumb_pc_offset(-2);
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calculate_flags_sub(dest, _sa, _sb);
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calculate_flags_sub(dest, _sa, _sb, 1);
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}
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break;
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