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35 Commits

Author SHA1 Message Date
David Guillen Fandos 401adca6ae Cleanup unused stuff in mips and arm 2021-09-15 20:34:21 +02:00
David Guillen Fandos 33f1e25099 Emit BIOS SWI entrypoint to ROM arena 
This fixes a race condition that happens whenever the ROM cache is flushed but
the RAM one is not, causing any SWI calls (implemented as direct branches) to
jump to random instructions.
The fix could be to flush both caches at the same time (~expensive on
low mem platforms), use indirect jumps (a bit expensive) or emit the SWI
handler below the watermark to ensure it is never flushed. This is cheap
and effective, requires minimal changes.
 2021-09-10 00:30:55 +02:00
David Guillen Fandos f51ed9de13 Improve SWI codepaths and implement div&divarm natively 2021-09-03 01:01:37 +02:00
David Guillen Fandos f5232543f5 Improve tracing prints 2021-08-15 22:48:43 +02:00
David Guillen Fandos 057b80f8cc Fix a bug with BLH (half BL) on ARM 
This fixes issues on games from Camelot (GS2 and Mario Golf)
 2021-08-15 22:19:40 +02:00
David Guillen Fandos 5be5015338 Rearrange register layout and exclude useless regs from savestat 
This changes the savestate format once again.
 2021-08-15 21:07:20 +02:00
David Guillen Fandos ce14e2585b Fix and reenable Android arm 32 bit builds 
Removed the last bits of text relocations by moving all relevant RAMs to
the stub reachable area. This should be as fast or even faster than
previous code.
 2021-07-31 17:45:46 +02:00
David Guillen Fandos b3abefa7d9 Avoid using relocations in arm code 2021-07-31 00:20:18 +02:00
David Guillen Fandos ae2a656e66 Remove nested functions in arm dynarec 
Re-enable Android builds
 2021-07-27 00:47:54 +02:00
David Guillen Fandos ea2608812f Minor optimization 2021-05-19 20:11:35 +02:00
David Guillen Fandos aafde6de7b Add ROM mirroring and fix mult. cycle count 
This should correct some minor issues in some games.
 2021-05-17 01:16:56 +02:00
David Guillen Fandos 37430f22c5 Small optimization (~2-4%) and whitespace cleanup! 
Cleans up a ton of whitespace in cpu.c (like 100KB!) and improves
readability of some massive decode statements.

Added an optimization for PC-relative loads (pool load) in ROM (since
it's read only and cannot possibily change) that directly emits an
immediate load. This is way faster, specially in MIPS/x86, ARM can be
even faster if we rewrite the immediate load macros to also use a pool.
 2021-05-07 20:41:54 +02:00
David Guillen Fandos 883f07f487 Fix small buf and add cheat error messages 
Some minor formating too
 2021-05-05 21:15:27 +02:00
David Guillen Fandos 4fd456e158 Adding Code Breaker cheat support 
This works on both interpreter and dynarec.
Tested in MIPS, ARM and x86, still needs some more testing, some edge
cases can be buggy.
 2021-05-05 21:15:27 +02:00
David Guillen Fandos d83f8fbd25 Fix Vita port and likely some Linux/Android hidden issues 
Using an invalid SP makes Vita crash (for an unkown reason) and makes
things like C signal handlers crash (luckily Retroarch doesn't use
them). It is also a violation of the ABI and not a great idea.
Recycled some little used registers to free SP. Perf should be roughly
the same.
 2021-04-27 18:39:46 +02:00
David Guillen Fandos 5b5a4db6c2 Add instruction tracing, for testing purposes 2021-04-03 00:37:42 +02:00
David Guillen Fandos 34e672ed25 Simplify open load handling for MIPS and fix other arches 
Also rewrite a bit memory handlers for smaller functions.
 2021-03-16 22:58:58 +01:00
David Guillen Fandos 7bebd3051c Remove dead code 
Turns out this was not even used! No need to fix it then!
 2021-03-05 01:15:55 +01:00
David Guillen Fandos 8d52e613c7 Minor cleanup in ARM and MIPS 
Fix some small issues, mainly associated with undefined behaviour
expressions
 2021-02-12 21:47:35 +01:00
David Guillen Fandos 2c6026cfe5 Move r15 to reg_a0 (instead of reg_mem) 
I think this does not make a difference at all in the code, since PC is
treated in a special way anyway (reloaded with an immediate when read
and treated as an indirect branch when written). However for the sake of
completeness I'm undoing what I did. (The comma fix stays :P)
 2021-02-10 02:53:26 +01:00
David Guillen Fandos 7aaa280b9f Fix ARM dynarec 
Turns out there were a couple of very interesting and hard to track
bugs. A missing comma made the reg list too short, leaving the 31th
element at the mercy of the linker ordering algorithm, which seems to
work in some cases depending on the compiler version.
Also the cache flush code seemed not to work on my machine (OGA),
not sure why it wored in the past :/
 2021-02-10 02:46:45 +01:00
twinaphex 679006a296 Add more forward declarations 2020-10-08 15:51:24 +02:00
twinaphex 4181385f39 Add forward declarations 2020-10-08 15:47:37 +02:00
Francisco José García García 6bfb7e1b47 (VITA) Dynarec working 2016-10-03 20:19:11 +02:00
Francisco José García García 44b63e7d28 (VITA) Dynarec WIP 2016-08-14 18:28:25 +02:00
Francisco José García García 6ab0992ecf (VITA) Dynarec WIP 2016-08-08 00:31:21 +02:00
Twinaphex d10c4afea2 Get rid of function_cc 2014-12-20 09:14:38 +01:00
twinaphex 5b59ef3acc Reimplement cache invalidation code 2014-12-11 18:47:48 +01:00
aliaspider a926a68eb3 cleanups 2014-12-10 12:53:26 +01:00
twinaphex fe19474dca Add macro parameter 'opcode' to some macros 2014-12-10 01:17:37 +01:00
aliaspider 9f97113292 fix compiler error: initializer element is not a compile-time constant 2014-12-10 00:20:41 +01:00
notaz c95affa70d merge an assorment of calc84maniac's fixes. 2012-09-18 01:30:43 +03:00
notaz 804e743b41 handle div by 0 2011-09-08 01:39:47 +03:00
notaz bbba320911 enable -Wall and fix warnings reported by it 2011-09-06 00:18:06 +03:00
notaz d5e0983c10 move platform-independent stuff out of /gp2x. 2011-09-02 17:44:41 +03:00
Renamed from gp2x/arm_emit.h (Browse further)