Add forward declarations
This commit is contained in:
twinaphex
parent
27419bc0b0
commit
4181385f39
214
arm/arm_emit.h
214
arm/arm_emit.h
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@ -22,13 +22,17 @@
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#include "arm_codegen.h"
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void generate_indirect_branch_arm(void);
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u32 prepare_load_reg_pc(u32 scratch_reg, u32 reg_index, u32 pc_offset);
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void generate_store_reg(u32 ireg, u32 reg_index);
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u32 arm_update_gba_arm(u32 pc);
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u32 arm_update_gba_thumb(u32 pc);
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u32 arm_update_gba_idle_arm(u32 pc);
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u32 arm_update_gba_idle_thumb(u32 pc);
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// Although these are defined as a function, don't call them as
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// such (jump to it instead)
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/* Although these are defined as a function, don't call them as
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* such (jump to it instead) */
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void arm_indirect_branch_arm(u32 address);
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void arm_indirect_branch_thumb(u32 address);
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void arm_indirect_branch_dual_arm(u32 address);
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@ -37,7 +41,7 @@ void arm_indirect_branch_dual_thumb(u32 address);
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void execute_store_cpsr(u32 new_cpsr, u32 store_mask, u32 address);
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u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address);
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void execute_store_spsr(u32 new_cpsr, u32 store_mask);
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u32 execute_read_spsr();
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u32 execute_read_spsr(void);
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u32 execute_spsr_restore(u32 address);
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void execute_swi_arm(u32 pc);
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@ -53,8 +57,8 @@ void execute_store_u32_safe(u32 address, u32 source);
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(((((u32)offset - (u32)source) - 8) >> 2) & 0xFFFFFF) \
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// reg_base_offset is the amount of bytes after reg_base where the registers
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// actually begin.
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/* reg_base_offset is the amount of bytes after reg_base where the registers
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* actually begin. */
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#define reg_base_offset 1024
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@ -77,25 +81,26 @@ void execute_store_u32_safe(u32 address, u32 source);
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#define reg_rd ARMREG_R0
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// Register allocation layout for ARM and Thumb:
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// Map from a GBA register to a host ARM register. -1 means load it
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// from memory into one of the temp registers.
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/* Register allocation layout for ARM and Thumb:
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* Map from a GBA register to a host ARM register. -1 means load it
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* from memory into one of the temp registers.
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// The following registers are chosen based on statistical analysis
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// of a few games (see below), but might not be the best ones. Results
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// vary tremendously between ARM and Thumb (for obvious reasons), so
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// two sets are used. Take care to not call any function which can
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// overwrite any of these registers from the dynarec - only call
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// trusted functions in arm_stub.S which know how to save/restore
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// them and know how to transfer them to the C functions it calls
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// if necessary.
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* The following registers are chosen based on statistical analysis
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* of a few games (see below), but might not be the best ones. Results
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* vary tremendously between ARM and Thumb (for obvious reasons), so
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* two sets are used. Take care to not call any function which can
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* overwrite any of these registers from the dynarec - only call
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* trusted functions in arm_stub.S which know how to save/restore
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* them and know how to transfer them to the C functions it calls
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* if necessary.
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// The following define the actual registers available for allocation.
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// As registers are freed up add them to this list.
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* The following define the actual registers available for allocation.
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* As registers are freed up add them to this list.
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// Note that r15 is linked to the a0 temp reg - this register will
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// be preloaded with a constant upon read, and used to link to
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// indirect branch functions upon write.
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* Note that r15 is linked to the a0 temp reg - this register will
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* be preloaded with a constant upon read, and used to link to
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* indirect branch functions upon write.
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*/
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#define reg_x0 ARMREG_R3
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#define reg_x1 ARMREG_R4
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@ -148,22 +153,22 @@ r15: 0.091287% (-- 100.000000%)
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s32 arm_register_allocation[] =
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{
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reg_x0, // GBA r0
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reg_x1, // GBA r1
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mem_reg, // GBA r2
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mem_reg, // GBA r3
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mem_reg, // GBA r4
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mem_reg, // GBA r5
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reg_x2, // GBA r6
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mem_reg, // GBA r7
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mem_reg, // GBA r8
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reg_x3, // GBA r9
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mem_reg, // GBA r10
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mem_reg, // GBA r11
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reg_x4, // GBA r12
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mem_reg, // GBA r13
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reg_x5, // GBA r14
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reg_a0 // GBA r15
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reg_x0, /* GBA r0 */
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reg_x1, /* GBA r1 */
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mem_reg, /* GBA r2 */
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mem_reg, /* GBA r3 */
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mem_reg, /* GBA r4 */
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mem_reg, /* GBA r5 */
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reg_x2, /* GBA r6 */
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mem_reg, /* GBA r7 */
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mem_reg, /* GBA r8 */
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reg_x3, /* GBA r9 */
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mem_reg, /* GBA r10 */
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mem_reg, /* GBA r11 */
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reg_x4, /* GBA r12 */
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mem_reg, /* GBA r13 */
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reg_x5, /* GBA r14 */
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reg_a0 /* GBA r15 */
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mem_reg,
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mem_reg,
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@ -185,22 +190,22 @@ s32 arm_register_allocation[] =
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s32 thumb_register_allocation[] =
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{
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reg_x0, // GBA r0
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reg_x1, // GBA r1
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reg_x2, // GBA r2
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reg_x3, // GBA r3
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reg_x4, // GBA r4
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reg_x5, // GBA r5
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mem_reg, // GBA r6
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mem_reg, // GBA r7
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mem_reg, // GBA r8
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mem_reg, // GBA r9
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mem_reg, // GBA r10
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mem_reg, // GBA r11
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mem_reg, // GBA r12
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mem_reg, // GBA r13
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mem_reg, // GBA r14
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reg_a0 // GBA r15
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reg_x0, /* GBA r0 */
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reg_x1, /* GBA r1 */
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reg_x2, /* GBA r2 */
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reg_x3, /* GBA r3 */
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reg_x4, /* GBA r4 */
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reg_x5, /* GBA r5 */
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mem_reg, /* GBA r6 */
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mem_reg, /* GBA r7 */
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mem_reg, /* GBA r8 */
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mem_reg, /* GBA r9 */
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mem_reg, /* GBA r10 */
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mem_reg, /* GBA r11 */
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mem_reg, /* GBA r12 */
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mem_reg, /* GBA r13 */
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mem_reg, /* GBA r14 */
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reg_a0 /* GBA r15 */
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mem_reg,
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mem_reg,
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@ -220,19 +225,16 @@ s32 thumb_register_allocation[] =
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mem_reg,
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};
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#define arm_imm_lsl_to_rot(value) \
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(32 - value) \
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u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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{
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u32 store_count = 0;
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u32 left_shift = 0;
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// Otherwise it'll return 0 things to store because it'll never
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// find anything.
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/* Otherwise it'll return 0 things to store because it'll never
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* find anything. */
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if(imm == 0)
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{
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rotations[0] = 0;
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@ -240,7 +242,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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return 1;
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}
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// Find chunks of non-zero data at 2 bit alignments.
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/* Find chunks of non-zero data at 2 bit alignments. */
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while(1)
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{
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for(; left_shift < 32; left_shift += 2)
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@ -249,20 +251,19 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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break;
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}
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/* We've hit the end of the useful data. */
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if(left_shift == 32)
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{
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// We've hit the end of the useful data.
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return store_count;
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}
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// Hit the end, it might wrap back around to the beginning.
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/* Hit the end, it might wrap back around to the beginning. */
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if(left_shift >= 24)
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{
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// Make a mask for the residual bits. IE, if we have
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// 5 bits of data at the end we can wrap around to 3
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// bits of data in the beginning. Thus the first
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// thing, after being shifted left, has to be less
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// than 111b, 0x7, or (1 << 3) - 1.
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/* Make a mask for the residual bits. IE, if we have
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* 5 bits of data at the end we can wrap around to 3
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* bits of data in the beginning. Thus the first
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* thing, after being shifted left, has to be less
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* than 111b, 0x7, or (1 << 3) - 1.
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*/
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u32 top_bits = 32 - left_shift;
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u32 residual_bits = 8 - top_bits;
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u32 residual_mask = (1 << residual_bits) - 1;
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@ -270,8 +271,8 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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if((store_count > 1) && (left_shift > 24) &&
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((stores[0] << ((32 - rotations[0]) & 0x1F)) < residual_mask))
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{
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// Then we can throw out the last bit and tack it on
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// to the first bit.
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/* Then we can throw out the last bit and tack it on
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* to the first bit. */
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stores[0] =
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(stores[0] << ((top_bits + (32 - rotations[0])) & 0x1F)) |
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((imm >> left_shift) & 0xFF);
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@ -281,7 +282,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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}
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else
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{
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// There's nothing to wrap over to in the beginning
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/* There's nothing to wrap over to in the beginning */
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stores[store_count] = (imm >> left_shift) & 0xFF;
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rotations[store_count] = (32 - left_shift) & 0x1F;
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return store_count + 1;
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@ -372,7 +373,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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#define generate_exit_block() \
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ARM_BX(0, ARMREG_LR) \
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// The branch target is to be filled in later (thus a 0 for now)
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/* The branch target is to be filled in later (thus a 0 for now) */
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#define generate_branch_filler(condition_code, writeback_location) \
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(writeback_location) = translation_ptr; \
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@ -412,9 +413,10 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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*((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) | \
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arm_relative_offset(dest, offset) \
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// A different function is called for idle updates because of the relative
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// location of the embedded PC. The idle version could be optimized to put
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// the CPU into halt mode too, however.
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/* A different function is called for idle updates because of the relative
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* location of the embedded PC. The idle version could be optimized to put
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* the CPU into halt mode too, however.
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*/
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#define generate_branch_idle_eliminate(writeback_location, new_pc, mode) \
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generate_function_call(arm_update_gba_idle_##mode); \
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@ -443,7 +445,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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generate_cycle_update(); \
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generate_branch_no_cycle_update(writeback_location, new_pc, mode) \
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// a0 holds the destination
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/* a0 holds the destination */
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#define generate_indirect_branch_no_cycle_update(type) \
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ARM_B(0, arm_relative_offset(translation_ptr, arm_indirect_branch_##type)) \
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@ -455,7 +457,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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#define generate_block_prologue() \
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#define generate_block_extra_vars_arm() \
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void generate_indirect_branch_arm() \
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void generate_indirect_branch_arm(void) \
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{ \
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if(condition == 0x0E) \
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{ \
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@ -639,9 +641,10 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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#define block_prologue_size 0
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// It should be okay to still generate result flags, spsr will overwrite them.
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// This is pretty infrequent (returning from interrupt handlers, et al) so
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// probably not worth optimizing for.
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/* It should be okay to still generate result flags, spsr will overwrite them.
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* This is pretty infrequent (returning from interrupt handlers, et al) so
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* probably not worth optimizing for.
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*/
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#define check_for_interrupts() \
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if((io_registers[REG_IE] & io_registers[REG_IF]) && \
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@ -927,9 +930,10 @@ u32 execute_spsr_restore_body(u32 pc)
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#define generate_op_mvns_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
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generate_op_reg_immshift_uflags(MVNS, _rd, _rm, shift_type, shift) \
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// The reg operand is in reg_rm, not reg_rn like expected, so rsbs isn't
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// being used here. When rsbs is fully inlined it can be used with the
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// apropriate operands.
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/* The reg operand is in reg_rm, not reg_rn like expected, so rsbs isn't
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* being used here. When rsbs is fully inlined it can be used with the
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* apropriate operands.
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*/
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#define generate_op_neg_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
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{ \
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@ -1092,7 +1096,7 @@ u32 execute_spsr_restore_body(u32 pc)
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#define arm_generate_op_reg_flags(name, load_op, store_op, flags_op) \
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arm_generate_op_reg(name, load_op, store_op, flags_op) \
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// imm will be loaded by the called function if necessary.
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/* imm will be loaded by the called function if necessary. */
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#define arm_generate_op_imm(name, load_op, store_op, flags_op) \
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arm_decode_data_proc_imm(opcode); \
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@ -1203,8 +1207,9 @@ u32 execute_spsr_restore_body(u32 pc)
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#define arm_psr_read(op_type, psr_reg) \
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arm_psr_read_##psr_reg() \
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// This function's okay because it's called from an ASM function that can
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// wrap it correctly.
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/* This function's okay because it's called from an ASM function that can
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* wrap it correctly.
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*/
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u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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{
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@ -1251,9 +1256,10 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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arm_psr_##transfer_type(op_type, psr_reg); \
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} \
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// TODO: loads will need the PC passed as well for open address, however can
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// eventually be rectified with a hash table on the memory accesses
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// (same with the stores)
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/* TODO: loads will need the PC passed as well for open address, however can
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* eventually be rectified with a hash table on the memory accesses
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* (same with the stores)
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*/
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#define arm_access_memory_load(mem_type) \
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cycle_count += 2; \
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@ -1267,7 +1273,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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generate_function_call(execute_store_##mem_type); \
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write32((pc + 4)) \
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// Calculate the address into a0 from _rn, _rm
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/* Calculate the address into a0 from _rn, _rm */
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#define arm_access_memory_adjust_reg_sh_up(ireg) \
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ARM_ADD_REG_IMMSHIFT(0, ireg, _rn, _rm, ((opcode >> 5) & 0x03), \
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@ -1365,7 +1371,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \
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// TODO: Make these use cached registers. Implement iwram_stack_optimize.
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/* TODO: Make these use cached registers. Implement iwram_stack_optimize. */
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#define arm_block_memory_load() \
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generate_function_call(execute_load_u32); \
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@ -1416,7 +1422,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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#define arm_block_memory_writeback_no()
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// Only emit writeback if the register is not in the list
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/* Only emit writeback if the register is not in the list */
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#define arm_block_memory_writeback_load(writeback_type) \
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if(!((reg_list >> rn) & 0x01)) \
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@ -1625,7 +1631,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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complete_store_reg(__rd, rd); \
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} \
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// Operation types: imm, mem_reg, mem_imm
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/* Operation types: imm, mem_reg, mem_imm */
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#define thumb_access_memory_load(mem_type, _rd) \
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cycle_count += 2; \
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@ -1663,7 +1669,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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thumb_access_memory_##access_type(mem_type, _rd); \
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} \
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// TODO: Make these use cached registers. Implement iwram_stack_optimize.
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/* TODO: Make these use cached registers. Implement iwram_stack_optimize. */
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#define thumb_block_address_preadjust_up() \
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generate_add_imm(reg_s0, (bit_count[reg_list] * 4), 0) \
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@ -1898,19 +1904,19 @@ u8 swi_hle_handle[256] =
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0x0 // SWI 2A: SoundGetJumpList
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};
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void execute_swi_hle_div_arm();
|
||||
void execute_swi_hle_div_thumb();
|
||||
void execute_swi_hle_div_arm(void);
|
||||
void execute_swi_hle_div_thumb(void);
|
||||
|
||||
void execute_swi_hle_div_c()
|
||||
void execute_swi_hle_div_c(void)
|
||||
{
|
||||
if (reg[1] == 0)
|
||||
// real BIOS supposedly locks up, but game can recover on interrupt
|
||||
return;
|
||||
s32 result = (s32)reg[0] / (s32)reg[1];
|
||||
reg[1] = (s32)reg[0] % (s32)reg[1];
|
||||
reg[0] = result;
|
||||
/* real BIOS supposedly locks up, but game can recover on interrupt */
|
||||
if (reg[1] == 0)
|
||||
return;
|
||||
s32 result = (s32)reg[0] / (s32)reg[1];
|
||||
reg[1] = (s32)reg[0] % (s32)reg[1];
|
||||
reg[0] = result;
|
||||
|
||||
reg[3] = (result ^ (result >> 31)) - (result >> 31);
|
||||
reg[3] = (result ^ (result >> 31)) - (result >> 31);
|
||||
}
|
||||
|
||||
#define generate_swi_hle_handler(_swi_number, mode) \
|
||||
|
|
|
|||
Loading…
Reference in New Issue