8c14ac9619
Add function decorators for easier debugging / profiling
2021-04-02 02:10:00 +02:00
71ebc49b59
Improve indirect jumps in ARM
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Handle already translated blocks in the ARM asm to speed up indirect
branches (affect some games more than others)
2021-03-30 21:06:52 +02:00
336b14a876
Improve ARM store handlers
2021-03-30 01:21:48 +02:00
fd20793545
Add CROSS_COMPILE rules
2021-03-27 15:09:01 +01:00
08d2fa1ebe
Merge pull request #120 from davidgfnet/master
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Fixes and improvements for MIPS and ARM
2021-03-27 00:31:51 +01:00
452ba76ba8
Fix 16 bit RAM stores (VRAM and OAM) in ARM
2021-03-26 23:13:26 +01:00
d284c868e9
Improve ARM store accesses
2021-03-26 23:13:26 +01:00
7ea6c5e247
Move OAM RAM to stubs also
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Makes accesses more efficient for MIPS. Make accesses also fast for palette
reads.
2021-03-26 23:13:26 +01:00
a494a3f00e
Move OAM update flag to a register
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Fix a small bug in MIPS dynarec that affects non -G0 targets
2021-03-26 23:13:26 +01:00
53cc4a2475
Merge pull request #119 from jdgleaver/dingux-beta-fix
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Fix OpenDingux Beta build
2021-03-26 17:32:51 +01:00
3db35eab70
Fix OpenDingux Beta build
2021-03-26 16:03:46 +00:00
6f2d0bbee8
Add od-beta
2021-03-25 21:21:21 +01:00
e5c685583e
Merge pull request #118 from davidgfnet/master
2021-03-23 20:13:44 +01:00
ff510e7f7a
Move caches to stub files to get around gcc 10
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Seems that using the __atribute__ magic for sections is not the best way
of doing this, since it injects some default atributtes that collide
with the user defined ones. Using assembly is far easier in this case.
Reworked definitions a bit to make it easier to import from assembly.
Also wrapped stuff around macros for easy and less verbose
implementation of the symbol prefix issue.
2021-03-23 20:02:44 +01:00
f31fa6a57b
Merge pull request #117 from davidgfnet/asmfixes2
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Make ewram memory linear
2021-03-23 19:43:20 +01:00
11ec213c99
Make ewram memory lineal
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This saves a few cycles in MIPS and simplifies a bit the core.
Removed the write map, only affects interpreter performance very
minimally. Rewired ARM and x86 handlers to support direct access to
I/EWRAM (and VRAM on ARM) to compensate. Overall performance is slightly
better but code is cleaner and allows for further improvements in the
dynarecs.
2021-03-23 19:09:56 +01:00
7e27010a3c
Merge pull request #116 from davidgfnet/master
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Export double symbol to cover Win but also Apple compilers
2021-03-23 01:00:27 +01:00
55eaee631d
Export double symbol to cover Win but also Apple compilers
2021-03-23 00:50:34 +01:00
128ad07777
Merge pull request #115 from davidgfnet/master
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Fix Windows compilers symbol names
2021-03-22 23:27:36 +01:00
8c18c8c421
Fix Windows compilers symbol names
2021-03-22 23:17:24 +01:00
f3ce8bbd0c
Merge pull request #114 from davidgfnet/master
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Adding Normmatt's BIOS as a built-in BIOS
2021-03-22 22:18:13 +01:00
f6f3a91039
Adding Normmatt's BIOS as a built-in BIOS
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Add options to select whether to boot from BIOS (default is no, as it is
now) and whether to use the original bios or the builtin one (default is
auto, which tries to use the official but falls back to the builtin if
not found).
2021-03-22 21:45:52 +01:00
5ef784ab8a
Merge pull request #112 from davidgfnet/master
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Enable runtime dynarec enable/disable
2021-03-18 03:15:03 +01:00
11632ad5e3
Merge pull request #113 from davidgfnet/asmfixes2
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asm fixes for clang
2021-03-18 03:14:55 +01:00
9de4220376
asm fixes for clang
2021-03-18 01:20:14 +01:00
eab44b9e0b
Enable runtime dynarec enable/disable
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Added a more thorough cache cleanup for reset/mode-change too.
Fixed the mmap initialization that ends up leaking memory.
Minor x86 asm fixes for Android.
2021-03-17 21:05:49 +01:00
3dfdaaa8d9
Merge pull request #111 from davidgfnet/master
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Remove BIOS reserved translation area
2021-03-17 19:09:12 +01:00
fb7ca09b01
Remove BIOS reserved translation area
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This is not really necessary since it can share area with ROM.
Performance impact should be very minimal (haven't noticed it myself)
and could be compensated (even by a positive offset) if we bump the ROM
cache area size.
Tested with several dynarecs.
2021-03-17 18:33:02 +01:00
85ba903b19
Merge pull request #110 from davidgfnet/master
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Rewrite the MIPS stub backend to add OpenDingux
2021-03-17 07:20:55 +01:00
34e672ed25
Simplify open load handling for MIPS and fix other arches
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Also rewrite a bit memory handlers for smaller functions.
2021-03-16 22:58:58 +01:00
6b503667ec
Add Dingux support
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Uses a different cache primitive and a differend madd(u) encoding.
Also added a flag for BGR vs RGB color output (since PSP is assuming to
be BGR for speed).
Aside from that the ABI required some special function calls for PIC.
2021-03-16 22:58:58 +01:00
80be1e3447
Remove old handlers from mips/stub
2021-03-16 22:58:58 +01:00
5ffd2832e8
Rewrite of the MIPS dynarec stubs
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This allows us to emit the handlers directly in a more efficient manner.
At the same time it allows for an easy fix to emit PIC code, which is
necessary for libretro. This also enables more platform specific
optimizations and variations, perhaps even run-time multiplatform
support.
2021-03-16 22:58:58 +01:00
b9ac453675
Merge pull request #109 from jdgleaver/post-process-fix
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Ensure post processing configuration is correctly reset in retro_deinit()
2021-03-16 14:24:29 +01:00
3db8eba7fd
Ensure post processing configuration is correctly reset in retro_deinit()
2021-03-16 13:14:21 +00:00
9551d76484
Merge pull request #108 from davidgfnet/master
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Move a few more registers to context
2021-03-16 02:09:41 +01:00
46cad2958a
Move a few more registers to context
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This gets rid of some more absolute addrs in the MIPS dynarec.
Tested on several platforms, we should be good.
2021-03-16 01:02:10 +01:00
bfc7cc7fdf
Merge pull request #107 from davidgfnet/master
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Move palettes around to simplify MIPS dynarec
2021-03-15 02:33:30 +01:00
c86b9064df
Move palettes around to simplify MIPS dynarec
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Will move also OAM structures to gain a few cycles per load/store.
Loads can also be optimized for an extra instruction per access.
2021-03-15 02:25:02 +01:00
6e9104e1ee
Merge pull request #105 from davidgfnet/master
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Fix typo
2021-03-12 23:19:10 +01:00
1f63b39523
Fix typo
2021-03-12 23:15:03 +01:00
8d60fb2507
Merge pull request #104 from davidgfnet/master
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Improve and simplify dynarec JIT area.
2021-03-12 22:36:33 +01:00
1e8097ac79
Improve and simplify dynarec JIT area.
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Also fix a regression on VITA.
Use gcc/OS cache flushing routines for MIPS32 instead of synci
2021-03-12 18:05:48 +01:00
e178b25425
Merge pull request #103 from davidgfnet/cachestuff
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Improve cache flush magic
2021-03-12 05:35:17 +01:00
7d25898439
Merge pull request #102 from davidgfnet/master
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Remove PSP-specific stuff from MIPS backend
2021-03-12 01:52:53 +01:00
462f0e9784
Improve cache flush magic
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Make it better and more generic. Add support for MIPS32 and fix the
messy PSP code.
2021-03-12 01:46:09 +01:00
7db08a3fcf
Fix fd check
2021-03-11 22:13:32 +01:00
5127f4b5cc
Remove PSP-specific stuff from MIPS backend
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This is unnecessary since newlib supports all file I/O.
This is needed for other mips ports
2021-03-10 18:41:37 +01:00
bd36c9c77d
Add osx-arm64 target
2021-03-09 22:05:36 +01:00
45c8ef0a0b
Merge pull request #101 from davidgfnet/master
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Remove libco
2021-03-09 20:31:50 +01:00
David Guillen Fandos
twinaphex
jdgleaver