Commit Graph

22 Commits

Author SHA1 Message Date
David Guillen Fandos 4fd456e158 Adding Code Breaker cheat support
This works on both interpreter and dynarec.
Tested in MIPS, ARM and x86, still needs some more testing, some edge
cases can be buggy.
2021-05-05 21:15:27 +02:00
David Guillen Fandos 5bee4d66c2 Do not use stack in mips stubs
No need for it (faster) and avoid mis-aligning it across calls
2021-04-03 23:43:32 +02:00
David Guillen Fandos 7ea6c5e247 Move OAM RAM to stubs also
Makes accesses more efficient for MIPS. Make accesses also fast for palette
reads.
2021-03-26 23:13:26 +01:00
David Guillen Fandos a494a3f00e Move OAM update flag to a register
Fix a small bug in MIPS dynarec that affects non -G0 targets
2021-03-26 23:13:26 +01:00
David Guillen Fandos ff510e7f7a Move caches to stub files to get around gcc 10
Seems that using the __atribute__ magic for sections is not the best way
of doing this, since it injects some default atributtes that collide
with the user defined ones. Using assembly is far easier in this case.

Reworked definitions a bit to make it easier to import from assembly.
Also wrapped stuff around macros for easy and less verbose
implementation of the symbol prefix issue.
2021-03-23 20:02:44 +01:00
David Guillen Fandos 11ec213c99 Make ewram memory lineal
This saves a few cycles in MIPS and simplifies a bit the core.
Removed the write map, only affects interpreter performance very
minimally. Rewired ARM and x86 handlers to support direct access to
I/EWRAM (and VRAM on ARM) to compensate. Overall performance is slightly
better but code is cleaner and allows for further improvements in the
dynarecs.
2021-03-23 19:09:56 +01:00
David Guillen Fandos 6b503667ec Add Dingux support
Uses a different cache primitive and a differend madd(u) encoding.
Also added a flag for BGR vs RGB color output (since PSP is assuming to
be BGR for speed).
Aside from that the ABI required some special function calls for PIC.
2021-03-16 22:58:58 +01:00
David Guillen Fandos 80be1e3447 Remove old handlers from mips/stub 2021-03-16 22:58:58 +01:00
David Guillen Fandos 5ffd2832e8 Rewrite of the MIPS dynarec stubs
This allows us to emit the handlers directly in a more efficient manner.
At the same time it allows for an easy fix to emit PIC code, which is
necessary for libretro. This also enables more platform specific
optimizations and variations, perhaps even run-time multiplatform
support.
2021-03-16 22:58:58 +01:00
David Guillen Fandos 46cad2958a Move a few more registers to context
This gets rid of some more absolute addrs in the MIPS dynarec.
Tested on several platforms, we should be good.
2021-03-16 01:02:10 +01:00
David Guillen Fandos c86b9064df Move palettes around to simplify MIPS dynarec
Will move also OAM structures to gain a few cycles per load/store.
Loads can also be optimized for an extra instruction per access.
2021-03-15 02:25:02 +01:00
David Guillen Fandos 1f63b39523 Fix typo 2021-03-12 23:15:03 +01:00
David Guillen Fandos 1e8097ac79 Improve and simplify dynarec JIT area.
Also fix a regression on VITA.
Use gcc/OS cache flushing routines for MIPS32 instead of synci
2021-03-12 18:05:48 +01:00
David Guillen Fandos 462f0e9784 Improve cache flush magic
Make it better and more generic. Add support for MIPS32 and fix the
messy PSP code.
2021-03-12 01:46:09 +01:00
David Guillen Fandos 56dc6ecb70 Remove libco
This removes libco and all the usages of it (+pthreads).
Rewired all dynarecs and interpreter to return after every frame so that
libretro can process events. This required to make dynarec re-entrant.

Dynarecs were updated to check for new frame on every update (IRQ, cycle
exhaustion, I/O write, etc). The performance impact of doing so should
be minimal (and definitely outweight the libco gains). While at it,
fixed small issues to get a bit more perf: arm dynarec was not idling
correctly, mips was using stack when not needed, etc.

Tested on PSP (mips), OGA (armv7), Linux (x86 and interpreter). Not
tested on Android though.
2021-03-08 18:44:03 +01:00
David Guillen Fandos 02e35339ee Fix a ghost bug with some games
Affects at least SM Adv 4 on PSP, which doesn't load at all.
I think the MIPS pipeline does not like invalidating the Icache and
using it immediately after (seems to read an old value sometimes?).
Rewired it to not do that and instead jump to the handler directly.
2021-03-08 02:59:11 +01:00
David Guillen Fandos f6ead0812a Remove more dead code 2021-02-26 18:36:57 +01:00
David Guillen Fandos ed3ba2c18b More cleanups (mostly whitespace and unused stuff) 2021-02-15 21:51:49 +01:00
David Guillen Fandos 8d52e613c7 Minor cleanup in ARM and MIPS
Fix some small issues, mainly associated with undefined behaviour
expressions
2021-02-12 21:47:35 +01:00
bmaupin a60de42f3a Get dynarec working again for PSP 2019-10-20 14:58:51 -04:00
aliaspider a926a68eb3 cleanups 2014-12-10 12:53:26 +01:00
notaz 2823a4c819 original source from gpsp09-2xb_src.tar.bz2 2009-05-21 18:48:31 +03:00