lifning
/
gpsp
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
gpsp/gpsp_config.h

31 lines
890 B
C
Raw Normal View History

Move caches to stub files to get around gcc 10 Seems that using the __atribute__ magic for sections is not the best way of doing this, since it injects some default atributtes that collide with the user defined ones. Using assembly is far easier in this case. Reworked definitions a bit to make it easier to import from assembly. Also wrapped stuff around macros for easy and less verbose implementation of the symbol prefix issue.
2021-03-23 19:47:51 +01:00
#ifndef GPSP_CONFIG_H
#define GPSP_CONFIG_H
Add overridable memory config knob for low-mem platforms
2021-07-21 00:10:30 +02:00
/* Default ROM buffer size in megabytes (this is a maximum value!) */
#ifndef ROM_BUFFER_SIZE
Rewrite ROM buffer allocation This improves the existing on-demand ROM paging and also breaks down ROM buffers into 1MB blocks for platforms with memory fragmentation issues. Fixed some potential RTC reg issue in said platforms too. Fixed page pinning on interpreter (would crash due to LRU evictions).
2021-07-14 01:17:55 +02:00
#define ROM_BUFFER_SIZE 32
Add overridable memory config knob for low-mem platforms
2021-07-21 00:10:30 +02:00
#endif
Rewrite ROM buffer allocation This improves the existing on-demand ROM paging and also breaks down ROM buffers into 1MB blocks for platforms with memory fragmentation issues. Fixed some potential RTC reg issue in said platforms too. Fixed page pinning on interpreter (would crash due to LRU evictions).
2021-07-14 01:17:55 +02:00
Move caches to stub files to get around gcc 10 Seems that using the __atribute__ magic for sections is not the best way of doing this, since it injects some default atributtes that collide with the user defined ones. Using assembly is far easier in this case. Reworked definitions a bit to make it easier to import from assembly. Also wrapped stuff around macros for easy and less verbose implementation of the symbol prefix issue.
2021-03-23 19:47:51 +01:00
/* Cache sizes and their config knobs */
Add support for RS90
2021-07-23 18:50:44 +02:00
#if defined(SMALL_TRANSLATION_CACHE)
Rework ram block ptrs to remove second indirection table. This removes ram_block_ptrs and encodes the pointer directly in the block tag. Saves ~256KB at no performance cost. Drawback is that it limits the ram cache size to 512KB (we were using 768KB before). Should not be a problem since most games use less than 32KB of cache anyway. Fixed ARM routines accordingly.
2021-07-08 21:29:48 +02:00
#define ROM_TRANSLATION_CACHE_SIZE (1024 * 1024 * 2)
Move caches to stub files to get around gcc 10 Seems that using the __atribute__ magic for sections is not the best way of doing this, since it injects some default atributtes that collide with the user defined ones. Using assembly is far easier in this case. Reworked definitions a bit to make it easier to import from assembly. Also wrapped stuff around macros for easy and less verbose implementation of the symbol prefix issue.
2021-03-23 19:47:51 +01:00
#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384)
Rework ram block ptrs to remove second indirection table. This removes ram_block_ptrs and encodes the pointer directly in the block tag. Saves ~256KB at no performance cost. Drawback is that it limits the ram cache size to 512KB (we were using 768KB before). Should not be a problem since most games use less than 32KB of cache anyway. Fixed ARM routines accordingly.
2021-07-08 21:29:48 +02:00
#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 2)
Move caches to stub files to get around gcc 10 Seems that using the __atribute__ magic for sections is not the best way of doing this, since it injects some default atributtes that collide with the user defined ones. Using assembly is far easier in this case. Reworked definitions a bit to make it easier to import from assembly. Also wrapped stuff around macros for easy and less verbose implementation of the symbol prefix issue.
2021-03-23 19:47:51 +01:00
#else
Rework ram block ptrs to remove second indirection table. This removes ram_block_ptrs and encodes the pointer directly in the block tag. Saves ~256KB at no performance cost. Drawback is that it limits the ram cache size to 512KB (we were using 768KB before). Should not be a problem since most games use less than 32KB of cache anyway. Fixed ARM routines accordingly.
2021-07-08 21:29:48 +02:00
#define ROM_TRANSLATION_CACHE_SIZE (1024 * 1024 * 10)
#define RAM_TRANSLATION_CACHE_SIZE (1024 * 512)
#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 8)
Move caches to stub files to get around gcc 10 Seems that using the __atribute__ magic for sections is not the best way of doing this, since it injects some default atributtes that collide with the user defined ones. Using assembly is far easier in this case. Reworked definitions a bit to make it easier to import from assembly. Also wrapped stuff around macros for easy and less verbose implementation of the symbol prefix issue.
2021-03-23 19:47:51 +01:00
#endif
Rework ram block ptrs to remove second indirection table. This removes ram_block_ptrs and encodes the pointer directly in the block tag. Saves ~256KB at no performance cost. Drawback is that it limits the ram cache size to 512KB (we were using 768KB before). Should not be a problem since most games use less than 32KB of cache anyway. Fixed ARM routines accordingly.
2021-07-08 21:29:48 +02:00
/* Please note that RAM_TRANSLATION_CACHE_SIZE is limited to 512KB
Check cpu_threaded.c for "memory tagging" for more info. */
Move caches to stub files to get around gcc 10 Seems that using the __atribute__ magic for sections is not the best way of doing this, since it injects some default atributtes that collide with the user defined ones. Using assembly is far easier in this case. Reworked definitions a bit to make it easier to import from assembly. Also wrapped stuff around macros for easy and less verbose implementation of the symbol prefix issue.
2021-03-23 19:47:51 +01:00
/* This is MIPS specific for now */
#define STUB_ARENA_SIZE (16*1024)
/* Hash table size for ROM trans cache lookups */
#define ROM_BRANCH_HASH_SIZE (1024 * 64)
#endif