[Interp] Improve sbit emulation for LDM
This commit is contained in:
David Guillen Fandos
parent
beb6e4b520
commit
f0f0b57c56
167
cpu.cc
167
cpu.cc
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@ -595,7 +595,6 @@ const u8 bit_count[256] =
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} \
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#define arm_spsr_restore() \
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if(rd == 15) \
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{ \
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if(reg[CPU_MODE] != MODE_USER && reg[CPU_MODE] != MODE_SYSTEM) \
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{ \
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@ -609,6 +608,18 @@ const u8 bit_count[256] =
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goto thumb_loop; \
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} \
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#define arm_spsr_restore_check() \
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if(rd == REG_PC) \
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{ \
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arm_spsr_restore() \
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} \
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#define arm_spsr_restore_ldm_check() \
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if (opcode & 0x8000) /* PC is in the LDM reg list */ \
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{ \
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arm_spsr_restore() \
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} \
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#define arm_data_proc_flags_reg() \
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arm_decode_data_proc_reg(opcode); \
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calculate_reg_sh_flags() \
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@ -648,7 +659,7 @@ const u8 bit_count[256] =
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calculate_flags_logic(dest); \
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arm_pc_offset(-4); \
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reg[rd] = dest; \
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arm_spsr_restore(); \
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arm_spsr_restore_check(); \
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} \
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#define arm_data_proc_add_flags(src_a, src_b, src_c, type) \
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@ -664,7 +675,7 @@ const u8 bit_count[256] =
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calculate_flags_add(dest, _sa, _sb); \
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arm_pc_offset(-4); \
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reg[rd] = dest; \
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arm_spsr_restore(); \
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arm_spsr_restore_check(); \
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}
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#define arm_data_proc_sub_flags(src_a, src_b, src_c, type) \
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@ -677,7 +688,7 @@ const u8 bit_count[256] =
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calculate_flags_sub(dest, _sa, _sb, _sc); \
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arm_pc_offset(-4); \
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reg[rd] = dest; \
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arm_spsr_restore(); \
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arm_spsr_restore_check(); \
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} \
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#define arm_data_proc_test_logic(expr, type) \
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@ -971,7 +982,7 @@ inline cpu_alert_type exec_arm_block_mem(u32 rn, u32 reglist, s32 &cycles_remain
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// However for LDM {PC} we restore CPSR from SPSR.
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// TODO: implement CPSR restore, only USER mode is now implemented.
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u32 old_cpsr = reg[REG_CPSR];
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if (sbit)
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if (sbit && (mode == AccStore || rn != REG_PC))
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set_cpu_mode(MODE_USER);
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// If base is in the reglist and writeback is enabled, the value of the
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@ -1010,7 +1021,7 @@ inline cpu_alert_type exec_arm_block_mem(u32 rn, u32 reglist, s32 &cycles_remain
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if (writeback && !writeback_first)
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reg[rn] = endaddr;
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if (sbit)
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if (sbit && (mode == AccStore || rn != REG_PC))
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set_cpu_mode(cpu_modes[old_cpsr & 0xF]);
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return cpu_alert;
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@ -2857,65 +2868,65 @@ arm_loop:
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x82: /* STMDA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, true, false, AddrDec, AddrUpdPost>(
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case 0x88: /* STMIA rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x84: /* STMDA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrDec, AddrUpdPost>(
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case 0x90: /* STMDB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x86: /* STMDA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrDec, AddrUpdPost>(
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case 0x98: /* STMIB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x88: /* STMIA rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrInc, AddrUpdPost>(
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case 0x82: /* STMDA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, true, false, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8A: /* STMIA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, true, false, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8C: /* STMIA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8E: /* STMIA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x90: /* STMDB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x92: /* STMDB rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, true, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x94: /* STMDB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x96: /* STMDB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x98: /* STMIB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9A: /* STMIB rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, true, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x84: /* STMDA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8C: /* STMIA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x94: /* STMDB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9C: /* STMIB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x86: /* STMDA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8E: /* STMIA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x96: /* STMDB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9E: /* STMIB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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@ -2928,68 +2939,76 @@ arm_loop:
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x83: /* LDMDA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, false, AddrDec, AddrUpdPost>(
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case 0x89: /* LDMIA rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x85: /* LDMDA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrDec, AddrUpdPost>(
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case 0x91: /* LDMDB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x87: /* LDMDA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrDec, AddrUpdPost>(
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case 0x99: /* LDMIB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x89: /* LDMIA rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrInc, AddrUpdPost>(
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case 0x83: /* LDMDA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, false, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8B: /* LDMIA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, false, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8D: /* LDMIA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8F: /* LDMIA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x91: /* LDMDB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x93: /* LDMDB rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x95: /* LDMDB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x97: /* LDMDB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x99: /* LDMIB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9B: /* LDMIB rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x85: /* LDMDA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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arm_spsr_restore_ldm_check();
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break;
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case 0x8D: /* LDMIA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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arm_spsr_restore_ldm_check();
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break;
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case 0x95: /* LDMDB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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arm_spsr_restore_ldm_check();
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break;
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case 0x9D: /* LDMIB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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arm_spsr_restore_ldm_check();
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break;
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case 0x87: /* LDMDA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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arm_spsr_restore_ldm_check();
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break;
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case 0x8F: /* LDMIA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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arm_spsr_restore_ldm_check();
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break;
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case 0x97: /* LDMDB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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arm_spsr_restore_ldm_check();
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break;
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case 0x9F: /* LDMIB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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arm_spsr_restore_ldm_check();
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break;
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