[Interp] Re-implement LDM/STM improving some missing cases.
Fixes the "base register in the list" for STM and partially honors the S bit.
This commit is contained in:
David Guillen Fandos
parent
723d23adf8
commit
beb6e4b520
397
cpu.cc
397
cpu.cc
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@ -17,10 +17,6 @@
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// Important todo:
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// - stm reglist writeback when base is in the list needs adjustment
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// - block memory needs psr swapping and user mode reg swapping
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extern "C" {
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#include "common.h"
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#include "cpu_instrument.h"
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@ -951,79 +947,74 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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access_type##_memory_##mem_type(address, access_type##_reg_op); \
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} \
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#define word_bit_count(word) \
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(bit_count[word >> 8] + bit_count[word & 0xFF]) \
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// Excutes an LDM/STM instruction
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#define arm_block_writeback_load() \
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if(!((reg_list >> rn) & 0x01)) \
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{ \
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reg[rn] = address; \
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} \
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typedef enum { AccLoad, AccStore } AccMode;
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typedef enum { AddrInc, AddrDec } AddrMode;
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typedef enum { AddrUpdPre, AddrUpdPost } AddrUpMode;
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#define arm_block_writeback_store() \
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reg[rn] = address \
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template<AccMode mode, bool writeback, bool sbit, AddrMode addr_mode, AddrUpMode updm>
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inline cpu_alert_type exec_arm_block_mem(u32 rn, u32 reglist, s32 &cycles_remaining) {
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cpu_alert_type cpu_alert = CPU_ALERT_NONE;
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// Register register usage stats.
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using_register(arm, rn, memory_base);
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using_register_list(arm, reglist, 16);
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#define arm_block_writeback_yes(access_type) \
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arm_block_writeback_##access_type() \
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// Calcualte base address.
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u32 numops = (bit_count[reglist >> 8] + bit_count[reglist & 0xFF]);
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u32 base = reg[rn];
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u32 address = base & ~3U;
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s32 addr_off = (addr_mode == AddrInc) ? 4 : -4; // Address incr/decr amount.
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u32 endaddr = base + addr_off * numops;
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#define arm_block_writeback_no(access_type) \
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// If sbit is set, change to user mode and back, so to write the user regs.
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// However for LDM {PC} we restore CPSR from SPSR.
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// TODO: implement CPSR restore, only USER mode is now implemented.
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u32 old_cpsr = reg[REG_CPSR];
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if (sbit)
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set_cpu_mode(MODE_USER);
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#define load_block_memory(address, dest) \
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dest = readaddress32(address_region, (address + offset) & 0x7FFF) \
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// If base is in the reglist and writeback is enabled, the value of the
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// written register depends on the write cycle (ARM7TDM manual 4.11.6).
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// If the register is the first, the written value is the original value,
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// otherwise the update base register is written. For LDM loaded date
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// takes always precendence.
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bool wrbck_base = (1 << rn) & reglist;
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bool base_first = (((1 << rn) - 1) & reglist) == 0;
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bool writeback_first = (mode == AccLoad) || !(wrbck_base && base_first);
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#define store_block_memory(address, dest) \
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address32(address_region, (address + offset) & 0x7FFF) = eswap32(dest) \
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if (writeback && writeback_first)
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reg[rn] = endaddr;
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#define arm_block_memory_offset_down_a() \
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(base - (word_bit_count(reg_list) * 4) + 4) \
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arm_pc_offset(4); // Advance PC
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#define arm_block_memory_offset_down_b() \
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(base - (word_bit_count(reg_list) * 4)) \
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for (u32 i = 0; i < 16; i++) {
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u32 regnum = (addr_mode == AddrInc) ? i : 15 - i;
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if ((reglist >> regnum) & 0x01) {
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// Update address for pre-update mode.
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if (updm == AddrUpdPre)
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address += addr_off;
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#define arm_block_memory_offset_no() \
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(base) \
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if (mode == AccLoad) {
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load_aligned32(address, reg[regnum]);
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} else {
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store_aligned32(address, (regnum == REG_PC) ? reg[REG_PC] + 4 : reg[regnum]);
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}
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#define arm_block_memory_offset_up() \
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(base + 4) \
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// Update address for post-update mode.
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if (updm == AddrUpdPost)
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address += addr_off;
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}
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}
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#define arm_block_memory_writeback_down() \
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reg[rn] = base - (word_bit_count(reg_list) * 4) \
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if (writeback && !writeback_first)
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reg[rn] = endaddr;
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#define arm_block_memory_writeback_up() \
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reg[rn] = base + (word_bit_count(reg_list) * 4) \
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if (sbit)
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set_cpu_mode(cpu_modes[old_cpsr & 0xF]);
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#define arm_block_memory_writeback_no() \
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#define arm_block_memory_load_pc() \
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load_aligned32(address, reg[REG_PC]); \
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#define arm_block_memory_store_pc() \
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store_aligned32(address, reg[REG_PC] + 4) \
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#define arm_block_memory(access_type, offset_type, writeback_type, s_bit) \
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{ \
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arm_decode_block_trans(); \
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u32 base = reg[rn]; \
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u32 address = arm_block_memory_offset_##offset_type() & 0xFFFFFFFC; \
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u32 i; \
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\
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arm_block_memory_writeback_##writeback_type(); \
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\
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for(i = 0; i < 15; i++) \
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{ \
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if((reg_list >> i) & 0x01) \
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{ \
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access_type##_aligned32(address, reg[i]); \
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address += 4; \
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} \
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} \
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\
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arm_pc_offset(4); \
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if(reg_list & 0x8000) \
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{ \
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arm_block_memory_##access_type##_pc(); \
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} \
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} \
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return cpu_alert;
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}
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#define arm_swap(type) \
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{ \
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@ -2860,165 +2851,147 @@ arm_loop:
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arm_access_memory(load, + reg_offset, reg, u8, yes, no_op);
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break;
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case 0x80:
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/* STMDA rn, rlist */
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arm_block_memory(store, down_a, no, no);
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break;
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/* STM instructions: STMDA, STMIA, STMDB, STMIB */
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case 0x81:
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/* LDMDA rn, rlist */
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arm_block_memory(load, down_a, no, no);
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break;
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case 0x80: /* STMDA rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x82: /* STMDA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, true, false, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x84: /* STMDA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x86: /* STMDA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x82:
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/* STMDA rn!, rlist */
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arm_block_memory(store, down_a, down, no);
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break;
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case 0x88: /* STMIA rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8A: /* STMIA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, true, false, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8C: /* STMIA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8E: /* STMIA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x83:
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/* LDMDA rn!, rlist */
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arm_block_memory(load, down_a, down, no);
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break;
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case 0x90: /* STMDB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x92: /* STMDB rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, true, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x94: /* STMDB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x96: /* STMDB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x84:
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/* STMDA rn, rlist^ */
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arm_block_memory(store, down_a, no, yes);
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break;
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case 0x98: /* STMIB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, false, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9A: /* STMIB rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccStore, true, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9C: /* STMIB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, false, true, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9E: /* STMIB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccStore, true, true, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x85:
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/* LDMDA rn, rlist^ */
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arm_block_memory(load, down_a, no, yes);
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break;
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case 0x86:
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/* STMDA rn!, rlist^ */
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arm_block_memory(store, down_a, down, yes);
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break;
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/* LDM instructions: LDMDA, LDMIA, LDMDB, LDMIB */
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case 0x87:
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/* LDMDA rn!, rlist^ */
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arm_block_memory(load, down_a, down, yes);
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break;
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case 0x81: /* LDMDA rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x83: /* LDMDA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, false, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x85: /* LDMDA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x87: /* LDMDA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrDec, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x88:
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/* STMIA rn, rlist */
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arm_block_memory(store, no, no, no);
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break;
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case 0x89: /* LDMIA rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8B: /* LDMIA rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, false, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8D: /* LDMIA rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8F: /* LDMIA rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrInc, AddrUpdPost>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x89:
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/* LDMIA rn, rlist */
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arm_block_memory(load, no, no, no);
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break;
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case 0x91: /* LDMDB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x93: /* LDMDB rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, false, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x95: /* LDMDB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x97: /* LDMDB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrDec, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8A:
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/* STMIA rn!, rlist */
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arm_block_memory(store, no, up, no);
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break;
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case 0x99: /* LDMIB rn, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9B: /* LDMIB rn!, rlist */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, false, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9D: /* LDMIB rn, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, false, true, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x9F: /* LDMIB rn!, rlist^ */
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cpu_alert |= exec_arm_block_mem<AccLoad, true, true, AddrInc, AddrUpdPre>(
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(opcode >> 16) & 0x0F, opcode & 0xFFFF, cycles_remaining);
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break;
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case 0x8B:
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/* LDMIA rn!, rlist */
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arm_block_memory(load, no, up, no);
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break;
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case 0x8C:
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/* STMIA rn, rlist^ */
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arm_block_memory(store, no, no, yes);
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break;
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case 0x8D:
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/* LDMIA rn, rlist^ */
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arm_block_memory(load, no, no, yes);
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break;
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case 0x8E:
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/* STMIA rn!, rlist^ */
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arm_block_memory(store, no, up, yes);
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break;
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case 0x8F:
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/* LDMIA rn!, rlist^ */
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arm_block_memory(load, no, up, yes);
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break;
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case 0x90:
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/* STMDB rn, rlist */
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arm_block_memory(store, down_b, no, no);
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break;
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case 0x91:
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/* LDMDB rn, rlist */
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arm_block_memory(load, down_b, no, no);
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break;
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case 0x92:
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/* STMDB rn!, rlist */
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arm_block_memory(store, down_b, down, no);
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break;
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case 0x93:
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/* LDMDB rn!, rlist */
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arm_block_memory(load, down_b, down, no);
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break;
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case 0x94:
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/* STMDB rn, rlist^ */
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arm_block_memory(store, down_b, no, yes);
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break;
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case 0x95:
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/* LDMDB rn, rlist^ */
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arm_block_memory(load, down_b, no, yes);
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break;
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case 0x96:
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/* STMDB rn!, rlist^ */
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arm_block_memory(store, down_b, down, yes);
|
||||
break;
|
||||
|
||||
case 0x97:
|
||||
/* LDMDB rn!, rlist^ */
|
||||
arm_block_memory(load, down_b, down, yes);
|
||||
break;
|
||||
|
||||
case 0x98:
|
||||
/* STMIB rn, rlist */
|
||||
arm_block_memory(store, up, no, no);
|
||||
break;
|
||||
|
||||
case 0x99:
|
||||
/* LDMIB rn, rlist */
|
||||
arm_block_memory(load, up, no, no);
|
||||
break;
|
||||
|
||||
case 0x9A:
|
||||
/* STMIB rn!, rlist */
|
||||
arm_block_memory(store, up, up, no);
|
||||
break;
|
||||
|
||||
case 0x9B:
|
||||
/* LDMIB rn!, rlist */
|
||||
arm_block_memory(load, up, up, no);
|
||||
break;
|
||||
|
||||
case 0x9C:
|
||||
/* STMIB rn, rlist^ */
|
||||
arm_block_memory(store, up, no, yes);
|
||||
break;
|
||||
|
||||
case 0x9D:
|
||||
/* LDMIB rn, rlist^ */
|
||||
arm_block_memory(load, up, no, yes);
|
||||
break;
|
||||
|
||||
case 0x9E:
|
||||
/* STMIB rn!, rlist^ */
|
||||
arm_block_memory(store, up, up, yes);
|
||||
break;
|
||||
|
||||
case 0x9F:
|
||||
/* LDMIB rn!, rlist^ */
|
||||
arm_block_memory(load, up, up, yes);
|
||||
break;
|
||||
|
||||
case 0xA0 ... 0xAF:
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue