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Remove CHANGED_PC_STATUS, simplify update flow

This commit is contained in:
David Guillen Fandos 2023-04-24 20:24:03 +02:00
parent 64b19d1301
commit eb50c15b1c
10 changed files with 51 additions and 69 deletions
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18
arm/arm64_stub.S
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@ -57,14 +57,9 @@ _##symbol:
#define REG_Z_FLAG (21 * 4)
#define REG_C_FLAG (22 * 4)
#define REG_V_FLAG (23 * 4)
#define CHANGED_PC_STATUS (24 * 4)
#define COMPLETED_FRAME (25 * 4)
#define OAM_UPDATED (26 * 4)
#define REG_SAVE (27 * 4)
#define REG_SAVE2 (28 * 4)
#define REG_SAVE3 (29 * 4)
#define REG_SAVE4 (30 * 4)
#define REG_SAVE5 (31 * 4)
#define COMPLETED_FRAME (24 * 4)
#define OAM_UPDATED (25 * 4)
#define REG_SAVE (26 * 4)
#define CPU_ALERT_HALT_B 0
#define CPU_ALERT_SMC_B 1
@ -162,11 +157,10 @@ defsymbl(a64_update_gba)
cbnz w1, return_to_main
// Resume execution (perhaps from a new PC)
mov reg_cycles, w0 // load new cycle count
and reg_cycles, w0, 0x7fff // load new cycle count
extract_flags(w2) // reload flag cache bits
ldr w0, [reg_base, #CHANGED_PC_STATUS] // see if PC has change
cbnz w0, 1f // go start from new PC
tbnz w0, #31, 1f // check if PC changed
ldr lr, [reg_base, #REG_SAVE] // Restore return point
load_registers() // reload registers
@ -712,7 +706,7 @@ write_epilogue:
alert_loop:
mov w0, reg_cycles // load remaining cycles
bl update_gba // update GBA until CPU isn't halted
mov reg_cycles, w0 // load new cycle count
and reg_cycles, w0, 0x7fff // load new cycle count
ldr w1, [reg_base, #COMPLETED_FRAME] // Check whether a frame was completed
cbnz w1, return_to_main // and return to caller function.

17
arm/arm_stub.S
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@ -39,14 +39,8 @@ _##symbol:
#define REG_Z_FLAG (21 * 4)
#define REG_C_FLAG (22 * 4)
#define REG_V_FLAG (23 * 4)
#define CHANGED_PC_STATUS (24 * 4)
#define COMPLETED_FRAME (25 * 4)
#define OAM_UPDATED (26 * 4)
#define REG_SAVE (27 * 4)
#define REG_SAVE2 (28 * 4)
#define REG_SAVE3 (29 * 4)
#define REG_SAVE4 (30 * 4)
#define REG_SAVE5 (31 * 4)
#define COMPLETED_FRAME (24 * 4)
#define OAM_UPDATED (25 * 4)
#define CPU_ALERT_HALT (1 << 0)
#define CPU_ALERT_SMC (1 << 1)
@ -205,10 +199,10 @@ defsymbl(arm_update_gba_##name) ;\
cmp r1, #0 ;\
bne return_to_main ;\
;\
mvn reg_cycles, r0 /* load new cycle count */;\
bic reg_cycles, r0, #0x80000000 /* clear MSB, not part of count */;\
mvn reg_cycles, reg_cycles /* we count negative to zero */;\
;\
ldr r0, [reg_base, #CHANGED_PC_STATUS] /* load PC changed status */;\
cmp r0, #0 /* see if PC has changed */;\
tst r0, #0x80000000 /* set if PC changed */;\
bne 1f /* go jump/translate */;\
;\
load_registers_##mode() /* reload registers */;\
@ -698,6 +692,7 @@ write_epilogue:
alert_loop:
call_c_function(update_gba) @ update GBA until CPU isn't halted
bic r0, r0, #0x80000000 @ clear MSB, not part of count
ldr r1, [reg_base, #COMPLETED_FRAME] @ Check whether a frame was completed
cmp r1, #0

12
cpu.c
View File

@ -1484,7 +1484,7 @@ cpu_alert_type check_interrupt() {
// Checks for pending IRQs and raises them. This changes the CPU mode
// which means that it must be called with a valid CPU state.
void check_and_raise_interrupts()
u32 check_and_raise_interrupts()
{
// Check any IRQ flag pending, IME and CPSR-IRQ enabled
if (cpu_has_interrupt())
@ -1500,8 +1500,9 @@ void check_and_raise_interrupts()
set_cpu_mode(MODE_IRQ);
reg[CPU_HALT_STATE] = CPU_ACTIVE;
reg[CHANGED_PC_STATUS] = 1;
return 1;
}
return 0;
}
// This function marks a pending interrupt but does not raise it.
@ -1560,7 +1561,7 @@ void execute_arm(u32 cycles)
{
/* Do not execute until CPU is active */
while(reg[CPU_HALT_STATE] != CPU_ACTIVE) {
cycles_remaining = update_gba(cycles_remaining);
cycles_remaining = update_gba_cycles(cycles_remaining);
if (reg[COMPLETED_FRAME])
return;
@ -3154,7 +3155,7 @@ skip_instruction:
} while(cycles_remaining > 0);
collapse_flags();
cycles_remaining = update_gba(cycles_remaining);
cycles_remaining = update_gba_cycles(cycles_remaining);
if (reg[COMPLETED_FRAME])
return;
continue;
@ -3671,7 +3672,7 @@ thumb_loop:
} while(cycles_remaining > 0);
collapse_flags();
cycles_remaining = update_gba(cycles_remaining);
cycles_remaining = update_gba_cycles(cycles_remaining);
if (reg[COMPLETED_FRAME])
return;
continue;
@ -3692,7 +3693,6 @@ void init_cpu(void)
spsr[i] = 0x00000010;
reg[CPU_HALT_STATE] = CPU_ACTIVE;
reg[CHANGED_PC_STATUS] = 0;
if (selected_boot_mode == boot_game) {
reg[REG_SP] = 0x03007F00;

18
cpu.h
View File

@ -91,14 +91,14 @@ typedef enum
REG_Z_FLAG = 21,
REG_C_FLAG = 22,
REG_V_FLAG = 23,
CHANGED_PC_STATUS = 24,
COMPLETED_FRAME = 25,
OAM_UPDATED = 26,
REG_SAVE = 27,
REG_SAVE2 = 28,
REG_SAVE3 = 29,
REG_SAVE4 = 30,
REG_SAVE5 = 31,
COMPLETED_FRAME = 24,
OAM_UPDATED = 25,
REG_SAVE = 26,
REG_SAVE2 = 27,
REG_SAVE3 = 28,
REG_SAVE4 = 29,
REG_SAVE5 = 30,
REG_SAVE6 = 31,
/* Machine defined storage */
REG_USERDEF = 32,
@ -109,7 +109,7 @@ typedef enum
extern u32 instruction_count;
void execute_arm(u32 cycles);
void check_and_raise_interrupts(void);
u32 check_and_raise_interrupts(void);
cpu_alert_type check_interrupt(void);
cpu_alert_type flag_interrupt(irq_type irq_raised);
void set_cpu_mode(cpu_mode_type new_mode);

7
main.c
View File

@ -109,6 +109,7 @@ void init_main(void)
u32 function_cc update_gba(int remaining_cycles)
{
u32 changed_pc = 0;
irq_type irq_raised = IRQ_NONE;
int dma_cycles;
trace_update_gba(remaining_cycles);
@ -124,7 +125,6 @@ u32 function_cc update_gba(int remaining_cycles)
cpu_ticks += completed_cycles;
remaining_cycles = 0;
reg[CHANGED_PC_STATUS] = 0;
reg[COMPLETED_FRAME] = 0;
if(gbc_sound_update)
@ -247,7 +247,8 @@ u32 function_cc update_gba(int remaining_cycles)
flag_interrupt(irq_raised);
// Raise any pending interrupts. This changes the CPU mode.
check_and_raise_interrupts();
if (check_and_raise_interrupts())
changed_pc = 0x80000000;
execute_cycles = MAX(video_count, 0);
@ -263,7 +264,7 @@ u32 function_cc update_gba(int remaining_cycles)
dma_cycles = MIN(64, dma_cycles);
dma_cycles = MIN(execute_cycles, dma_cycles);
return execute_cycles - dma_cycles;
return (execute_cycles - dma_cycles) | changed_pc;
}
void reset_gba(void)

1
main.h
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@ -76,6 +76,7 @@ extern u32 flush_ram_count;
extern char main_path[512];
extern char save_path[512];
#define update_gba_cycles(c) (update_gba(c) & 0x7FFF)
u32 function_cc update_gba(int remaining_cycles);
void reset_gba(void);

2
mips/mips_emit.h
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@ -1972,7 +1972,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
#define ReOff_SaveR2 (REG_SAVE2 * 4)
#define ReOff_SaveR3 (REG_SAVE3 * 4)
#define ReOff_OamUpd (OAM_UPDATED*4) // OAM_UPDATED
#define ReOff_GP_Save (REG_SAVE4 * 4) // GP_SAVE
#define ReOff_GP_Save (REG_SAVE5 * 4) // GP_SAVE
// Saves all regs to their right slot and loads gp
#define emit_save_regs(save_a2) { \

22
mips/mips_stub.S
View File

@ -104,12 +104,12 @@ symbol:
.equ REG_Z_FLAG, (21 * 4)
.equ REG_C_FLAG, (22 * 4)
.equ REG_V_FLAG, (23 * 4)
.equ CHANGED_PC_STATUS, (24 * 4)
.equ COMPLETED_FRAME, (25 * 4)
.equ OAM_UPDATED, (26 * 4)
.equ REG_SAVE, (27 * 4)
.equ REG_SAVE2, (28 * 4)
.equ REG_SAVE3, (29 * 4)
.equ COMPLETED_FRAME, (24 * 4)
.equ OAM_UPDATED, (25 * 4)
.equ REG_SAVE, (26 * 4)
.equ REG_SAVE2, (27 * 4)
.equ REG_SAVE3, (28 * 4)
.equ REG_SAVE4, (29 * 4)
.equ GP_SAVE, (30 * 4)
.equ GP_SAVE_HI, (31 * 4)
@ -247,21 +247,17 @@ defsymbl(mips_update_gba)
sw $ra, REG_SAVE2($16) # save return addr
collapse_flags # update cpsr
save_registers # save registers
sw $0, CHANGED_PC_STATUS($16)
move $4, reg_cycles # Remaining cycles as asg0
cfncall update_gba, 0 # process the next event
lw $1, COMPLETED_FRAME($16) # Check whether we completed a frame
bne $1, $0, return_to_main # Return to main thread now
move reg_cycles, $2 # update new cycle count (ret value)
and reg_cycles, $2, 0x7FFF # update new cycle count (ret value)
bltz $2, lookup_pc
lw $ra, REG_SAVE2($16) # restore return address
lw $1, CHANGED_PC_STATUS($16)
bne $1, $0, lookup_pc
nop
restore_registers
jr $ra # if not, go back to caller
@ -347,7 +343,7 @@ defsymbl(write_io_epilogue)
alert_loop:
move $4, reg_cycles # Remaining cycles as asg0
cfncall update_gba, 0 # process the next event
move reg_cycles, $2 # update new cycle count (ret value)
and reg_cycles, $2, 0x7FFF # update new cycle count (ret value)
lw $1, COMPLETED_FRAME($16) # Check whether we completed a frame
bne $1, $0, return_to_main # Return to main thread now

1
savestate.c
View File

@ -107,7 +107,6 @@ bool gba_load_state(const void* src)
#endif
instruction_count = 0;
reg[CHANGED_PC_STATUS] = 1;
reg[COMPLETED_FRAME] = 0;
reg[OAM_UPDATED] = 1;
gbc_sound_update = 1;

22
x86/x86_stub.S
View File

@ -95,14 +95,9 @@ _##symbol:
.equ REG_Z_FLAG, (21 * 4)
.equ REG_C_FLAG, (22 * 4)
.equ REG_V_FLAG, (23 * 4)
.equ CHANGED_PC_STATUS, (24 * 4)
.equ COMPLETED_FRAME, (25 * 4)
.equ OAM_UPDATED, (26 * 4)
.equ REG_SAVE, (27 * 4)
.equ REG_SAVE2, (28 * 4)
.equ REG_SAVE3, (29 * 4)
.equ REG_SAVE4, (30 * 4)
.equ REG_SAVE5, (31 * 4)
.equ COMPLETED_FRAME, (24 * 4)
.equ OAM_UPDATED, (25 * 4)
.equ REG_SAVE, (26 * 4)
.equ load_u8_tbl, -(9 * 16 * ADDR_SIZE_BYTES)
.equ load_s8_tbl, -(8 * 16 * ADDR_SIZE_BYTES)
@ -176,15 +171,16 @@ defsymbl(x86_update_gba)
mov REG_CYCLES, CARG1_REG # Load remaining cycles as arg0
CALL_FUNC(update_gba) # process the next event
mov %eax, REG_CYCLES # new cycle count
and $0x7fff, REG_CYCLES # in the lowest bits
# did we just complete a frame? go back to main then
cmpl $0, COMPLETED_FRAME(REG_BASE)
jne return_to_main
# did the PC change?
cmpl $1, CHANGED_PC_STATUS(REG_BASE)
je lookup_pc
ret # if not, go back to caller
test %eax, %eax # Bit 31 set, means need to re-fetch
js lookup_pc
ret # otherwise, go back to caller
# Perform this on an indirect branch that will definitely go to
# ARM code, IE anything that changes the PC in ARM mode except
@ -269,7 +265,8 @@ alert_loop:
mov REG_CYCLES, CARG1_REG # Load remaining cycles as arg0
CALL_FUNC(update_gba) # process the next event
mov %eax, REG_CYCLES # load new cycle count
and $0x7fff, REG_CYCLES # (only lowest bits)
# did we just complete a frame? go back to main then
cmpl $0, COMPLETED_FRAME(REG_BASE)
jne return_to_main
@ -502,7 +499,6 @@ defsymbl(execute_store_cpsr)
smc_write:
CALL_FUNC(flush_translation_cache_ram)
lookup_pc:
movl $0, CHANGED_PC_STATUS(REG_BASE) # Lookup new block and jump to it
mov REG_PC(REG_BASE), CARG1_REG # Load PC as argument0
testl $0x20, REG_CPSR(REG_BASE)
jz 1f