Improve and simplify 16 bit I/O writes too
This commit is contained in:
David Guillen Fandos
parent
a53399af58
commit
64b19d1301
240
gba_memory.c
240
gba_memory.c
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@ -718,238 +718,158 @@ static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
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return CPU_ALERT_NONE;
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}
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#define access_register16_high(address) \
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value = (value << 16) | (readaddress16(io_registers, address)) \
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#define access_register16_low(address) \
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value = ((readaddress16(io_registers, address + 2)) << 16) | value \
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static inline s32 signext28(u32 value)
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{
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s32 ret = (s32)(value << 4);
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return ret >> 4;
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}
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cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
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{
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uint16_t ioreg = (address & 0x3FE) >> 1;
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value &= 0xffff;
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switch(address)
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switch(ioreg)
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{
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case 0x00:
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{
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u32 dispcnt = read_ioreg(REG_DISPCNT);
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if((value & 0x07) != (dispcnt & 0x07))
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reg[OAM_UPDATED] = 1;
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case REG_DISPCNT:
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// Changing the lowest 3 bits might require object re-sorting
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reg[OAM_UPDATED] |= ((value & 0x07) != (read_ioreg(REG_DISPCNT) & 0x07));
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write_ioreg(REG_DISPCNT, value);
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break;
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}
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// DISPSTAT
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case 0x04:
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// DISPSTAT has 3 read only bits, controlled by the LCD controller
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case REG_DISPSTAT:
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write_ioreg(REG_DISPSTAT, (read_ioreg(REG_DISPSTAT) & 0x07) | (value & ~0x07));
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break;
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// VCOUNT
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case 0x06:
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break;
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// BG2 reference X
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case 0x28:
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access_register16_low(0x28);
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affine_reference_x[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x28) = eswap32(value);
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break;
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case 0x2A:
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access_register16_high(0x28);
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affine_reference_x[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x28) = eswap32(value);
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case REG_BG2X_L:
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case REG_BG2X_H:
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write_ioreg(ioreg, value);
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affine_reference_x[0] = signext28(read_ioreg32(REG_BG2X_L));
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break;
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// BG2 reference Y
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case 0x2C:
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access_register16_low(0x2C);
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affine_reference_y[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x2C) = eswap32(value);
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break;
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case 0x2E:
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access_register16_high(0x2C);
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affine_reference_y[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x2C) = eswap32(value);
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case REG_BG2Y_L:
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case REG_BG2Y_H:
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write_ioreg(ioreg, value);
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affine_reference_y[0] = signext28(read_ioreg32(REG_BG2Y_L));
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break;
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// BG3 reference X
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case 0x38:
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access_register16_low(0x38);
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affine_reference_x[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x38) = eswap32(value);
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break;
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case 0x3A:
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access_register16_high(0x38);
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affine_reference_x[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x38) = eswap32(value);
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case REG_BG3X_L:
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case REG_BG3X_H:
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write_ioreg(ioreg, value);
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affine_reference_x[1] = signext28(read_ioreg32(REG_BG3X_L));
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break;
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// BG3 reference Y
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case 0x3C:
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access_register16_low(0x3C);
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affine_reference_y[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x3C) = eswap32(value);
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case REG_BG3Y_L:
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case REG_BG3Y_H:
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write_ioreg(ioreg, value);
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affine_reference_y[1] = signext28(read_ioreg32(REG_BG3Y_L));
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break;
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case 0x3E:
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access_register16_high(0x3C);
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affine_reference_y[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x3C) = eswap32(value);
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break;
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// Sound 1 control sweep
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case 0x60:
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// Sound 1 registers
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case REG_SOUND1CNT_L: // control sweep
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gbc_sound_tone_control_sweep();
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break;
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// Sound 1 control duty/length/envelope
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case 0x62:
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case REG_SOUND1CNT_H: // control duty/length/envelope
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gbc_sound_tone_control_low(0, REG_SOUND1CNT_H);
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break;
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// Sound 1 control frequency
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case 0x64:
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case REG_SOUND1CNT_X: // control frequency
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gbc_sound_tone_control_high(0, REG_SOUND1CNT_X);
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break;
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// Sound 2 control duty/length/envelope
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case 0x68:
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// Sound 2 registers
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case REG_SOUND2CNT_L: // control duty/length/envelope
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gbc_sound_tone_control_low(1, REG_SOUND2CNT_L);
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break;
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// Sound 2 control frequency
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case 0x6C:
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case REG_SOUND2CNT_H: // control frequency
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gbc_sound_tone_control_high(1, REG_SOUND2CNT_H);
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break;
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// Sound 3 control wave
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case 0x70:
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// Sound 3 registers
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case REG_SOUND3CNT_L: // control wave
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gbc_sound_wave_control();
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break;
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// Sound 3 control length/volume
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case 0x72:
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case REG_SOUND3CNT_H: // control length/volume
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gbc_sound_tone_control_low_wave();
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break;
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// Sound 3 control frequency
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case 0x74:
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case REG_SOUND3CNT_X: // control frequency
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gbc_sound_tone_control_high_wave();
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break;
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// Sound 4 control length/envelope
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case 0x78:
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// Sound 4 registers
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case REG_SOUND4CNT_L: // length/envelope
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gbc_sound_tone_control_low(3, REG_SOUND4CNT_L);
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break;
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// Sound 4 control frequency
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case 0x7C:
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case REG_SOUND4CNT_H: // control frequency
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gbc_sound_noise_control();
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break;
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// Sound control L
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case 0x80:
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// Sound control registers
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case REG_SOUNDCNT_L:
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gbc_trigger_sound(value);
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break;
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// Sound control H
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case 0x82:
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case REG_SOUNDCNT_H:
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trigger_sound();
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break;
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// Sound control X
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case 0x84:
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case REG_SOUNDCNT_X:
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sound_control_x(value);
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break;
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// Sound wave RAM
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case 0x90 ... 0x9E:
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// Sound wave RAM, flag wave table update
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case REG_SOUNDWAVE_0 ... REG_SOUNDWAVE_7:
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gbc_sound_wave_update = 1;
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address16(io_registers, address) = eswap16(value);
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write_ioreg(ioreg, value);
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break;
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// DMA control
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case 0xBA:
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return trigger_dma(0, value);
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// DMA control register: can cause an IRQ
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case REG_DMA0CNT_H: return trigger_dma(0, value);
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case REG_DMA1CNT_H: return trigger_dma(1, value);
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case REG_DMA2CNT_H: return trigger_dma(2, value);
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case REG_DMA3CNT_H: return trigger_dma(3, value);
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case 0xC6:
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return trigger_dma(1, value);
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// Timer counter reload
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case REG_TM0D: count_timer(0); break;
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case REG_TM1D: count_timer(1); break;
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case REG_TM2D: count_timer(2); break;
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case REG_TM3D: count_timer(3); break;
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case 0xD2:
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return trigger_dma(2, value);
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/* Timer control register (0..3)*/
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case REG_TM0CNT: trigger_timer(0, value); break;
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case REG_TM1CNT: trigger_timer(1, value); break;
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case REG_TM2CNT: trigger_timer(2, value); break;
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case REG_TM3CNT: trigger_timer(3, value); break;
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case 0xDE:
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return trigger_dma(3, value);
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// Timer counts
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case 0x100:
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count_timer(0);
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break;
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case 0x104:
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count_timer(1);
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break;
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case 0x108:
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count_timer(2);
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break;
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case 0x10C:
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count_timer(3);
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break;
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/* Timer control 0 */
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case 0x102:
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trigger_timer(0, value);
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break;
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/* Timer control 1 */
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case 0x106:
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trigger_timer(1, value);
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break;
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/* Timer control 2 */
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case 0x10A:
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trigger_timer(2, value);
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break;
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/* Timer control 3 */
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case 0x10E:
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trigger_timer(3, value);
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break;
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// P1
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case 0x130:
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break;
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// REG_IE
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case 0x200:
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write_ioreg(REG_IE, value);
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return check_interrupt();
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// Interrupt flag
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case 0x202:
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// Interrupt flag, clears the bits it tries to write
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case REG_IF:
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write_ioreg(REG_IF, read_ioreg(REG_IF) & (~value));
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break;
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// WAITCNT
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case 0x204:
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write_ioreg(REG_WAITCNT, value);
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break;
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// REG_IME
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case 0x208:
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write_ioreg(REG_IME, value);
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// Register writes with side-effects, can raise an IRQ
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case REG_IE:
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case REG_IME:
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write_ioreg(ioreg, value);
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return check_interrupt();
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// Read-only registers
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case REG_P1:
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case REG_VCOUNT:
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break; // Do nothing
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// Registers without side effects
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case REG_WAITCNT:
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default:
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address16(io_registers, address) = eswap16(value);
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write_ioreg(ioreg, value);
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break;
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}
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@ -968,9 +888,9 @@ cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
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// Partial 16 bit write, treat like a regular merge-write
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if (address & 1)
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value = (value << 8) | (read_ioreg((address >> 1) & 0x1FF) & 0x00ff);
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value = (value << 8) | (read_ioreg(address >> 1) & 0x00ff);
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else
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value = (value & 0xff) | (read_ioreg((address >> 1) & 0x1FF) & 0xff00);
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value = (value & 0xff) | (read_ioreg(address >> 1) & 0xff00);
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return write_io_register16(address & 0x3FE, value);
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}
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