Simplify I/O byte writes
Can easily be mapped to 16 bit writes.
This commit is contained in:
David Guillen Fandos
parent
2d28451f6c
commit
a53399af58
1 changed files with 18 additions and 399 deletions
417
gba_memory.c
417
gba_memory.c
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@ -719,402 +719,12 @@ static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
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}
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#define access_register8_high(address) \
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value = (value << 8) | (address8(io_registers, address)) \
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#define access_register8_low(address) \
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value = ((address8(io_registers, address + 1)) << 8) | value \
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#define access_register16_high(address) \
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value = (value << 16) | (readaddress16(io_registers, address)) \
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#define access_register16_low(address) \
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value = ((readaddress16(io_registers, address + 2)) << 16) | value \
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cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
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{
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value &= 0xff;
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switch(address)
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{
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case 0x00:
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{
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u32 dispcnt = read_ioreg(REG_DISPCNT);
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if((value & 0x07) != (dispcnt & 0x07))
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reg[OAM_UPDATED] = 1;
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address8(io_registers, 0x00) = value;
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break;
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}
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// DISPSTAT (lower byte)
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case 0x04:
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address8(io_registers, 0x04) =
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(address8(io_registers, 0x04) & 0x07) | (value & ~0x07);
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break;
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// VCOUNT
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case 0x06:
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case 0x07:
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break;
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// BG2 reference X
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case 0x28:
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access_register8_low(0x28);
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access_register16_low(0x28);
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affine_reference_x[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x28) = eswap32(value);
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break;
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case 0x29:
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access_register8_high(0x28);
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access_register16_low(0x28);
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affine_reference_x[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x28) = eswap32(value);
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break;
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case 0x2A:
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access_register8_low(0x2A);
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access_register16_high(0x28);
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affine_reference_x[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x28) = eswap32(value);
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break;
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case 0x2B:
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access_register8_high(0x2A);
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access_register16_high(0x28);
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affine_reference_x[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x28) = eswap32(value);
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break;
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// BG2 reference Y
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case 0x2C:
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access_register8_low(0x2C);
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access_register16_low(0x2C);
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affine_reference_y[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x2C) = eswap32(value);
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break;
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case 0x2D:
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access_register8_high(0x2C);
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access_register16_low(0x2C);
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affine_reference_y[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x2C) = eswap32(value);
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break;
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case 0x2E:
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access_register8_low(0x2E);
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access_register16_high(0x2C);
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affine_reference_y[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x2C) = eswap32(value);
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break;
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case 0x2F:
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access_register8_high(0x2E);
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access_register16_high(0x2C);
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affine_reference_y[0] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x2C) = eswap32(value);
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break;
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// BG3 reference X
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case 0x38:
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access_register8_low(0x38);
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access_register16_low(0x38);
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affine_reference_x[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x38) = eswap32(value);
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break;
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case 0x39:
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access_register8_high(0x38);
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access_register16_low(0x38);
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affine_reference_x[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x38) = eswap32(value);
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break;
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case 0x3A:
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access_register8_low(0x3A);
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access_register16_high(0x38);
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affine_reference_x[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x38) = eswap32(value);
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break;
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case 0x3B:
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access_register8_high(0x3A);
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access_register16_high(0x38);
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affine_reference_x[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x38) = eswap32(value);
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break;
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// BG3 reference Y
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case 0x3C:
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access_register8_low(0x3C);
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access_register16_low(0x3C);
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affine_reference_y[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x3C) = eswap32(value);
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break;
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case 0x3D:
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access_register8_high(0x3C);
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access_register16_low(0x3C);
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affine_reference_y[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x3C) = eswap32(value);
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break;
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case 0x3E:
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access_register8_low(0x3E);
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access_register16_high(0x3C);
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affine_reference_y[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x3C) = eswap32(value);
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break;
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case 0x3F:
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access_register8_high(0x3E);
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access_register16_high(0x3C);
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affine_reference_y[1] = (s32)(value << 4) >> 4;
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address32(io_registers, 0x3C) = eswap32(value);
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break;
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// Sound 1 control sweep
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case 0x60:
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gbc_sound_tone_control_sweep();
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break;
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// Sound 1 control duty/length/envelope
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case 0x62:
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access_register8_low(0x62);
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gbc_sound_tone_control_low(0, REG_SOUND1CNT_H);
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break;
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case 0x63:
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access_register8_high(0x62);
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gbc_sound_tone_control_low(0, REG_SOUND1CNT_H);
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break;
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// Sound 1 control frequency
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case 0x64:
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access_register8_low(0x64);
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gbc_sound_tone_control_high(0, REG_SOUND1CNT_X);
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break;
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case 0x65:
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access_register8_high(0x64);
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gbc_sound_tone_control_high(0, REG_SOUND1CNT_X);
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break;
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// Sound 2 control duty/length/envelope
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case 0x68:
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access_register8_low(0x68);
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gbc_sound_tone_control_low(1, REG_SOUND2CNT_L);
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break;
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case 0x69:
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access_register8_high(0x68);
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gbc_sound_tone_control_low(1, REG_SOUND2CNT_L);
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break;
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// Sound 2 control frequency
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case 0x6C:
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access_register8_low(0x6C);
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gbc_sound_tone_control_high(1, REG_SOUND2CNT_H);
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break;
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case 0x6D:
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access_register8_high(0x6C);
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gbc_sound_tone_control_high(1, REG_SOUND2CNT_H);
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break;
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// Sound 3 control wave
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case 0x70:
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access_register8_low(0x70);
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gbc_sound_wave_control();
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break;
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case 0x71:
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access_register8_high(0x70);
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gbc_sound_wave_control();
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break;
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// Sound 3 control length/volume
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case 0x72:
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access_register8_low(0x72);
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gbc_sound_tone_control_low_wave();
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break;
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case 0x73:
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access_register8_high(0x72);
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gbc_sound_tone_control_low_wave();
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break;
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// Sound 3 control frequency
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case 0x74:
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access_register8_low(0x74);
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gbc_sound_tone_control_high_wave();
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break;
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case 0x75:
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access_register8_high(0x74);
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gbc_sound_tone_control_high_wave();
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break;
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// Sound 4 control length/envelope
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case 0x78:
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access_register8_low(0x78);
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gbc_sound_tone_control_low(3, REG_SOUND4CNT_L);
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break;
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case 0x79:
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access_register8_high(0x78);
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gbc_sound_tone_control_low(3, REG_SOUND4CNT_L);
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break;
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// Sound 4 control frequency
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case 0x7C:
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access_register8_low(0x7C);
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gbc_sound_noise_control();
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break;
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case 0x7D:
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access_register8_high(0x7C);
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gbc_sound_noise_control();
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break;
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// Sound control L
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case 0x80:
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access_register8_low(0x80);
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gbc_trigger_sound(value);
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break;
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case 0x81:
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access_register8_high(0x80);
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gbc_trigger_sound(value);
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break;
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// Sound control H
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case 0x82:
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access_register8_low(0x82);
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trigger_sound();
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break;
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case 0x83:
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access_register8_high(0x82);
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trigger_sound();
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break;
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// Sound control X
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case 0x84:
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sound_control_x(value);
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break;
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// Sound wave RAM
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case 0x90 ... 0x9F:
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gbc_sound_wave_update = 1;
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address8(io_registers, address) = value;
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break;
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// DMA control (trigger byte)
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case 0xBB:
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access_register8_low(0xBA);
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return trigger_dma(0, value);
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case 0xC7:
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access_register8_low(0xC6);
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return trigger_dma(1, value);
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case 0xD3:
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access_register8_low(0xD2);
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return trigger_dma(2, value);
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case 0xDF:
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access_register8_low(0xDE);
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return trigger_dma(3, value);
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// Timer counts
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case 0x100:
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access_register8_low(0x100);
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count_timer(0);
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break;
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case 0x101:
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access_register8_high(0x100);
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count_timer(0);
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break;
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case 0x104:
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access_register8_low(0x104);
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count_timer(1);
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break;
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case 0x105:
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access_register8_high(0x104);
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count_timer(1);
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break;
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case 0x108:
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access_register8_low(0x108);
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count_timer(2);
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break;
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case 0x109:
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access_register8_high(0x108);
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count_timer(2);
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break;
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case 0x10C:
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access_register8_low(0x10C);
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count_timer(3);
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break;
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case 0x10D:
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access_register8_high(0x10C);
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count_timer(3);
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break;
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// Timer control (trigger byte)
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case 0x103:
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access_register8_low(0x102);
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trigger_timer(0, value);
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break;
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case 0x107:
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access_register8_low(0x106);
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trigger_timer(1, value);
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break;
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case 0x10B:
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access_register8_low(0x10A);
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trigger_timer(2, value);
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break;
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case 0x10F:
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access_register8_low(0x10E);
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trigger_timer(3, value);
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break;
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// IF
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case 0x202:
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address8(io_registers, 0x202) &= ~value;
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break;
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case 0x203:
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address8(io_registers, 0x203) &= ~value;
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break;
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// Halt
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case 0x301:
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if((value & 0x01) == 0)
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reg[CPU_HALT_STATE] = CPU_HALT;
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else
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reg[CPU_HALT_STATE] = CPU_STOP;
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return CPU_ALERT_HALT;
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default:
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address8(io_registers, address) = value;
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break;
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}
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return CPU_ALERT_NONE;
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}
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cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
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{
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@ -1338,15 +948,6 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
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write_ioreg(REG_IME, value);
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return check_interrupt();
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// Halt
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case 0x300:
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if(((value >> 8) & 0x01) == 0)
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reg[CPU_HALT_STATE] = CPU_HALT;
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else
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reg[CPU_HALT_STATE] = CPU_STOP;
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return CPU_ALERT_HALT;
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default:
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address16(io_registers, address) = eswap16(value);
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break;
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@ -1355,6 +956,24 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
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return CPU_ALERT_NONE;
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}
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cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
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{
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if (address == 0x301) {
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if (value & 1)
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reg[CPU_HALT_STATE] = CPU_STOP;
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else
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reg[CPU_HALT_STATE] = CPU_HALT;
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return CPU_ALERT_HALT;
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}
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// Partial 16 bit write, treat like a regular merge-write
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if (address & 1)
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value = (value << 8) | (read_ioreg((address >> 1) & 0x1FF) & 0x00ff);
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else
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value = (value & 0xff) | (read_ioreg((address >> 1) & 0x1FF) & 0xff00);
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return write_io_register16(address & 0x3FE, value);
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}
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cpu_alert_type function_cc write_io_register32(u32 address, u32 value)
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{
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// Handle sound FIFO data write
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Add table
Reference in a new issue