Improve open bus reads on ARM/MIPS
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8c4196d19e
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@ -52,6 +52,7 @@ _##symbol:
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#define CPU_MODE (17 * 4)
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#define CPU_MODE (17 * 4)
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#define CPU_HALT_STATE (18 * 4)
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#define CPU_HALT_STATE (18 * 4)
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#define REG_BUS_VALUE (19 * 4)
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#define REG_N_FLAG (20 * 4)
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#define REG_N_FLAG (20 * 4)
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#define REG_Z_FLAG (21 * 4)
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#define REG_Z_FLAG (21 * 4)
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#define REG_C_FLAG (22 * 4)
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#define REG_C_FLAG (22 * 4)
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@ -324,6 +325,8 @@ defsymbl(execute_swi)
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store_registers()
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store_registers()
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mov w0, #MODE_SUPERVISOR
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mov w0, #MODE_SUPERVISOR
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bl set_cpu_mode // Set supervisor mode
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bl set_cpu_mode // Set supervisor mode
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ldr w0, =0xe3a02004
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str w0, [reg_base, REG_BUS_VALUE]
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ldr lr, [reg_base, #REG_SAVE]
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ldr lr, [reg_base, #REG_SAVE]
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load_registers()
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load_registers()
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ret
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ret
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@ -34,6 +34,7 @@ _##symbol:
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#define CPU_MODE (17 * 4)
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#define CPU_MODE (17 * 4)
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#define CPU_HALT_STATE (18 * 4)
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#define CPU_HALT_STATE (18 * 4)
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#define REG_BUS_VALUE (19 * 4)
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#define REG_N_FLAG (20 * 4)
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#define REG_N_FLAG (20 * 4)
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#define REG_Z_FLAG (21 * 4)
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#define REG_Z_FLAG (21 * 4)
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#define REG_C_FLAG (22 * 4)
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#define REG_C_FLAG (22 * 4)
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@ -387,6 +388,8 @@ defsymbl(execute_swi_##mode) ;\
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store_registers_##mode() /* store regs for mode */;\
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store_registers_##mode() /* store regs for mode */;\
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call_c_function(set_cpu_mode) /* set the CPU mode to svsr */;\
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call_c_function(set_cpu_mode) /* set the CPU mode to svsr */;\
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load_registers_arm() /* load ARM regs */;\
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load_registers_arm() /* load ARM regs */;\
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ldr r0, =0xe3a02004 /* Update open BUS value */;\
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str r0, [reg_base, #REG_BUS_VALUE] ;\
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;\
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;\
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restore_flags() ;\
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restore_flags() ;\
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add pc, lr, #4 /* return */;\
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add pc, lr, #4 /* return */;\
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16
cpu.c
16
cpu.c
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@ -959,7 +959,7 @@ const u32 psr_masks[16] =
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} \
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} \
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if(((_address >> 24) == 0) && (pc >= 0x4000)) \
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if(((_address >> 24) == 0) && (pc >= 0x4000)) \
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{ \
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{ \
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ror(dest, bios_read_protect, (_address & 0x03) << 3); \
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ror(dest, reg[REG_BUS_VALUE], (_address & 0x03) << 3); \
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} \
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} \
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else \
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else \
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\
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\
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@ -1577,7 +1577,7 @@ void raise_interrupt(irq_type irq_raised)
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((reg[REG_CPSR] & 0x80) == 0))
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((reg[REG_CPSR] & 0x80) == 0))
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{
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{
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// Value after the FIQ returns, should be improved
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// Value after the FIQ returns, should be improved
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bios_read_protect = 0xe55ec002;
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reg[REG_BUS_VALUE] = 0xe55ec002;
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// Interrupt handler in BIOS
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// Interrupt handler in BIOS
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reg_mode[MODE_IRQ][6] = reg[REG_PC] + 4;
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reg_mode[MODE_IRQ][6] = reg[REG_PC] + 4;
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@ -3197,7 +3197,7 @@ arm_loop:
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/* Jump to BIOS SWI handler */
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/* Jump to BIOS SWI handler */
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default:
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default:
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// After SWI, we read bios[0xE4]
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// After SWI, we read bios[0xE4]
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bios_read_protect = 0xe3a02004;
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reg[REG_BUS_VALUE] = 0xe3a02004;
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reg_mode[MODE_SUPERVISOR][6] = pc + 4;
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reg_mode[MODE_SUPERVISOR][6] = pc + 4;
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collapse_flags();
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collapse_flags();
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spsr[MODE_SUPERVISOR] = reg[REG_CPSR];
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spsr[MODE_SUPERVISOR] = reg[REG_CPSR];
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@ -3684,7 +3684,7 @@ thumb_loop:
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{
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{
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default:
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default:
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// After SWI, we read bios[0xE4]
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// After SWI, we read bios[0xE4]
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bios_read_protect = 0xe3a02004;
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reg[REG_BUS_VALUE] = 0xe3a02004;
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reg_mode[MODE_SUPERVISOR][6] = pc + 2;
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reg_mode[MODE_SUPERVISOR][6] = pc + 2;
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spsr[MODE_SUPERVISOR] = reg[REG_CPSR];
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spsr[MODE_SUPERVISOR] = reg[REG_CPSR];
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reg[REG_PC] = 0x00000008;
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reg[REG_PC] = 0x00000008;
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@ -3790,8 +3790,8 @@ void init_cpu(void)
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bool cpu_read_savestate(const u8 *src)
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bool cpu_read_savestate(const u8 *src)
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{
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{
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const u8 *cpudoc = bson_find_key(src, "cpu");
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const u8 *cpudoc = bson_find_key(src, "cpu");
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return bson_read_int32(cpudoc, "bus-value", &bios_read_protect) &&
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return bson_read_int32(cpudoc, "bus-value", ®[REG_BUS_VALUE]) &&
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bson_read_int32_array(cpudoc, "regs", reg, REG_IGNORE) &&
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bson_read_int32_array(cpudoc, "regs", reg, REG_ARCH_COUNT) &&
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bson_read_int32_array(cpudoc, "spsr", spsr, 6) &&
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bson_read_int32_array(cpudoc, "spsr", spsr, 6) &&
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bson_read_int32_array(cpudoc, "regmod", (u32*)reg_mode, 7*7);
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bson_read_int32_array(cpudoc, "regmod", (u32*)reg_mode, 7*7);
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}
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}
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@ -3800,10 +3800,10 @@ unsigned cpu_write_savestate(u8 *dst)
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{
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{
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u8 *wbptr, *startp = dst;
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u8 *wbptr, *startp = dst;
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bson_start_document(dst, "cpu", wbptr);
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bson_start_document(dst, "cpu", wbptr);
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bson_write_int32array(dst, "regs", reg, REG_IGNORE);
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bson_write_int32array(dst, "regs", reg, REG_ARCH_COUNT);
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bson_write_int32array(dst, "spsr", spsr, 6);
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bson_write_int32array(dst, "spsr", spsr, 6);
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bson_write_int32array(dst, "regmod", reg_mode, 7*7);
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bson_write_int32array(dst, "regmod", reg_mode, 7*7);
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bson_write_int32(dst, "bus-value", bios_read_protect);
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bson_write_int32(dst, "bus-value", reg[REG_BUS_VALUE]);
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bson_finish_document(dst, wbptr);
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bson_finish_document(dst, wbptr);
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return (unsigned int)(dst - startp);
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return (unsigned int)(dst - startp);
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5
cpu.h
5
cpu.h
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@ -74,7 +74,10 @@ typedef enum
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REG_CPSR = 16,
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REG_CPSR = 16,
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CPU_MODE = 17,
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CPU_MODE = 17,
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CPU_HALT_STATE = 18,
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CPU_HALT_STATE = 18,
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REG_IGNORE = 19,
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REG_ARCH_COUNT = 19,
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// This is saved separately
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REG_BUS_VALUE = 19,
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// Dynarec signaling and spilling
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// Dynarec signaling and spilling
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// (Not really part of the CPU state)
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// (Not really part of the CPU state)
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@ -305,7 +305,6 @@ const u32 gamepak_waitstate_sequential[2][3][3] =
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};
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};
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u8 bios_rom[1024 * 16];
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u8 bios_rom[1024 * 16];
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u32 bios_read_protect;
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// Up to 128kb, store SRAM, flash ROM, or EEPROM here.
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// Up to 128kb, store SRAM, flash ROM, or EEPROM here.
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u8 gamepak_backup[1024 * 128];
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u8 gamepak_backup[1024 * 128];
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@ -569,7 +568,7 @@ u32 function_cc read_eeprom(void)
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case 0x00: \
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case 0x00: \
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/* BIOS */ \
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/* BIOS */ \
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if(reg[REG_PC] >= 0x4000) \
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if(reg[REG_PC] >= 0x4000) \
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ror(value, bios_read_protect, (address & 0x03) << 3); \
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ror(value, reg[REG_BUS_VALUE], (address & 0x03) << 3); \
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else \
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else \
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value = readaddress##type(bios_rom, address & 0x3FFF); \
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value = readaddress##type(bios_rom, address & 0x3FFF); \
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break; \
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break; \
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@ -3030,7 +3029,7 @@ void init_memory(void)
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rtc_state = RTC_DISABLED;
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rtc_state = RTC_DISABLED;
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memset(rtc_registers, 0, sizeof(rtc_registers));
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memset(rtc_registers, 0, sizeof(rtc_registers));
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bios_read_protect = 0xe129f000;
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reg[REG_BUS_VALUE] = 0xe129f000;
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}
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}
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void memory_term(void)
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void memory_term(void)
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@ -209,7 +209,6 @@ extern u32 gbc_sound_wave_update;
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extern dma_transfer_type dma[DMA_CHAN_CNT];
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extern dma_transfer_type dma[DMA_CHAN_CNT];
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extern u8 open_gba_bios_rom[1024*16];
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extern u8 open_gba_bios_rom[1024*16];
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extern u32 bios_read_protect;
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extern u16 palette_ram[512];
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extern u16 palette_ram[512];
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extern u16 oam_ram[512];
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extern u16 oam_ram[512];
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extern u16 palette_ram_converted[512];
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extern u16 palette_ram_converted[512];
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@ -99,6 +99,7 @@ symbol:
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.equ CPU_MODE, (17 * 4)
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.equ CPU_MODE, (17 * 4)
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.equ CPU_HALT_STATE, (18 * 4)
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.equ CPU_HALT_STATE, (18 * 4)
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.equ REG_BUS_VALUE, (19 * 4)
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.equ REG_N_FLAG, (20 * 4)
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.equ REG_N_FLAG, (20 * 4)
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.equ REG_Z_FLAG, (21 * 4)
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.equ REG_Z_FLAG, (21 * 4)
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.equ REG_C_FLAG, (22 * 4)
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.equ REG_C_FLAG, (22 * 4)
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@ -420,8 +421,9 @@ defsymbl(execute_swi)
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cfncall set_cpu_mode, 5 # set the CPU mode to supervisor
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cfncall set_cpu_mode, 5 # set the CPU mode to supervisor
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lw $ra, REG_SAVE3($16)
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lw $ra, REG_SAVE3($16)
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restore_registers
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restore_registers
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la $2, 0xe3a02004 # Update open BUS value
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jr $ra # return
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jr $ra # return
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nop
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sw $2, REG_BUS_VALUE($16)
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# $4: pc to restore to
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# $4: pc to restore to
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# returns in $4
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# returns in $4
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@ -2134,7 +2134,7 @@ u32 execute_store_cpsr_body()
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static void function_cc execute_swi(u32 pc)
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static void function_cc execute_swi(u32 pc)
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{
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{
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// Open bus value after SWI
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// Open bus value after SWI
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bios_read_protect = 0xe3a02004;
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reg[REG_BUS_VALUE] = 0xe3a02004;
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reg_mode[MODE_SUPERVISOR][6] = pc;
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reg_mode[MODE_SUPERVISOR][6] = pc;
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spsr[MODE_SUPERVISOR] = reg[REG_CPSR];
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spsr[MODE_SUPERVISOR] = reg[REG_CPSR];
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// Move to ARM mode, supervisor mode, disable IRQs
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// Move to ARM mode, supervisor mode, disable IRQs
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@ -84,6 +84,7 @@ _##symbol:
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.equ CPU_MODE, (17 * 4)
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.equ CPU_MODE, (17 * 4)
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.equ CPU_HALT_STATE, (18 * 4)
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.equ CPU_HALT_STATE, (18 * 4)
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.equ REG_BUS_VALUE, (19 * 4)
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.equ REG_N_FLAG, (20 * 4)
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.equ REG_N_FLAG, (20 * 4)
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.equ REG_Z_FLAG, (21 * 4)
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.equ REG_Z_FLAG, (21 * 4)
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.equ REG_C_FLAG, (22 * 4)
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.equ REG_C_FLAG, (22 * 4)
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