Add MIPS codegen tests
This commit is contained in:
David Guillen Fandos
parent
81649a2c80
commit
8c4196d19e
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@ -19,38 +19,38 @@
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typedef enum
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{
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mips_reg_zero,
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mips_reg_at,
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mips_reg_v0,
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mips_reg_v1,
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mips_reg_a0,
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mips_reg_a1,
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mips_reg_a2,
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mips_reg_a3,
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mips_reg_t0,
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mips_reg_t1,
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mips_reg_t2,
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mips_reg_t3,
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mips_reg_t4,
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mips_reg_t5,
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mips_reg_t6,
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mips_reg_t7,
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mips_reg_s0,
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mips_reg_s1,
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mips_reg_s2,
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mips_reg_s3,
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mips_reg_s4,
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mips_reg_s5,
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mips_reg_s6,
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mips_reg_s7,
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mips_reg_t8,
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mips_reg_t9,
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mips_reg_k0,
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mips_reg_k1,
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mips_reg_gp,
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mips_reg_sp,
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mips_reg_fp,
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mips_reg_ra
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mips_reg_zero = 0,
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mips_reg_at = 1,
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mips_reg_v0 = 2,
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mips_reg_v1 = 3,
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mips_reg_a0 = 4,
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mips_reg_a1 = 5,
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mips_reg_a2 = 6,
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mips_reg_a3 = 7,
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mips_reg_t0 = 8,
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mips_reg_t1 = 9,
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mips_reg_t2 = 10,
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mips_reg_t3 = 11,
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mips_reg_t4 = 12,
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mips_reg_t5 = 13,
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mips_reg_t6 = 14,
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mips_reg_t7 = 15,
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mips_reg_s0 = 16,
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mips_reg_s1 = 17,
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mips_reg_s2 = 18,
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mips_reg_s3 = 19,
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mips_reg_s4 = 20,
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mips_reg_s5 = 21,
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mips_reg_s6 = 22,
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mips_reg_s7 = 23,
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mips_reg_t8 = 24,
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mips_reg_t9 = 25,
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mips_reg_k0 = 26,
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mips_reg_k1 = 27,
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mips_reg_gp = 28,
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mips_reg_sp = 29,
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mips_reg_fp = 30,
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mips_reg_ra = 31
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} mips_reg_number;
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typedef enum
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@ -216,12 +216,6 @@ typedef enum
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#define mips_emit_xor(rd, rs, rt) \
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mips_emit_special(xor, rs, rt, rd, 0) \
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#define mips_emit_add(rd, rs, rt) \
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mips_emit_special(and, rs, rt, rd, 0) \
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#define mips_emit_sub(rd, rs, rt) \
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mips_emit_special(sub, rs, rt, rd, 0) \
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#define mips_emit_and(rd, rs, rt) \
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mips_emit_special(and, rs, rt, rd, 0) \
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@ -359,10 +353,10 @@ typedef enum
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#define mips_emit_ins(rt, rs, pos, size) \
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mips_emit_special3(ins, rs, rt, (pos + size - 1), pos) \
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#define mips_emit_seb(rt, rd) \
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#define mips_emit_seb(rd, rt) \
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mips_emit_special3(bshfl, 0, rt, rd, mips_bshfl_seb) \
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#define mips_emit_seh(rt, rd) \
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#define mips_emit_seh(rd, rt) \
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mips_emit_special3(bshfl, 0, rt, rd, mips_bshfl_seh) \
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@ -407,6 +401,6 @@ typedef enum
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mips_emit_regimm(bltz, rs, offset) \
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#define mips_emit_nop() \
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mips_emit_sll(reg_zero, reg_zero, 0) \
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mips_emit_sll(mips_reg_zero, mips_reg_zero, 0) \
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@ -1904,8 +1904,8 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
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#define extract_bits(rt, rs, pos, size) \
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mips_emit_ext(rt, rs, pos, size)
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// Extends signed byte to u32
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#define extend_byte_signed(rt, rs) \
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mips_emit_seb(rt, rs)
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#define extend_byte_signed(rd, rs) \
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mips_emit_seb(rd, rs)
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// Rotates a word using a temp reg if necessary
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#define rotate_right(rdest, rsrc, rtemp, amount) \
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mips_emit_rotr(rdest, rsrc, amount);
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@ -1933,9 +1933,9 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
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mips_emit_sll(rt, rs, 32 - ((pos) + (size))); \
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mips_emit_srl(rt, rt, 32 - (size))
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// Extends signed byte to u32
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#define extend_byte_signed(rt, rs) \
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mips_emit_sll(rt, rs, 24); \
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mips_emit_sra(rt, rt, 24)
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#define extend_byte_signed(rd, rs) \
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mips_emit_sll(rd, rs, 24); \
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mips_emit_sra(rd, rd, 24)
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// Rotates a word (uses temp reg)
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#define rotate_right(rdest, rsrc, rtemp, amount) \
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mips_emit_sll(rtemp, rsrc, 32 - (amount)); \
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@ -1,5 +1,6 @@
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ARMV8PFX=/opt/buildroot-armv8el-uclibc/bin/aarch64-buildroot-linux-uclibc
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MIPS32PFX=/opt/buildroot-mipsel32-o32-uclibc/bin/mipsel-buildroot-linux-uclibc
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all:
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gcc -o arm64gen arm64gen.c -ggdb -I../arm/
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@ -8,5 +9,11 @@ all:
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$(ARMV8PFX)-objcopy -O binary bytecoderef.o bytecoderef.bin
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@ cmp bytecoderef.bin bytecode.bin || echo "Bytecode mismatch"
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@ cmp bytecoderef.bin bytecode.bin && echo "Test passed!"
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gcc -o mipsgen mipsgen.c -ggdb -I../mips/
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./mipsgen > bytecode.bin
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$(MIPS32PFX)-as -EL -o bytecoderef.o mipsgen.S
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$(MIPS32PFX)-objcopy -j .text -O binary bytecoderef.o bytecoderef.bin
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@ cmp bytecoderef.bin bytecode.bin || echo "Bytecode mismatch"
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@ cmp bytecoderef.bin bytecode.bin && echo "Test passed!"
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@ -0,0 +1,180 @@
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.set mips32r2
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.set noreorder
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.text
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nop
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nop
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# Generic MIPS insts
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addu $4, $5, $6
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addu $29, $31, $20
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subu $4, $5, $6
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subu $29, $31, $20
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xor $4, $5, $6
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xor $29, $31, $20
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and $4, $5, $6
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and $29, $31, $20
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or $4, $5, $6
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or $29, $31, $20
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nor $4, $5, $6
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nor $29, $31, $20
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slt $4, $5, $6
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slt $29, $31, $20
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sltu $4, $5, $6
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sltu $29, $31, $20
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sllv $4, $5, $6
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sllv $29, $31, $20
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srlv $4, $5, $6
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srlv $29, $31, $20
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srav $4, $5, $6
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srav $29, $31, $20
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rotrv $4, $5, $6
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rotrv $29, $31, $20
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sll $4, $5, 0
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srl $4, $5, 0
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sra $4, $5, 0
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rotr $4, $5, 0
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sll $4, $5, 1
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srl $4, $5, 1
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sra $4, $5, 1
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rotr $4, $5, 1
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sll $4, $5, 30
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srl $4, $5, 30
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sra $4, $5, 30
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rotr $4, $5, 30
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sll $4, $5, 31
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srl $4, $5, 31
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sra $4, $5, 31
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rotr $4, $5, 31
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lui $4, 0xFFFF
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lui $4, 0x8000
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lui $4, 0
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lui $4, 1
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addiu $4, $22, -1
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xori $4, $22, 0xFFFF
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ori $4, $22, 0xFFFF
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andi $4, $22, 0xFFFF
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slti $4, $22, -1
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sltiu $4, $22, -1
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addiu $4, $22, 0
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xori $4, $22, 0
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ori $4, $22, 0
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andi $4, $22, 0
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slti $4, $22, 0
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sltiu $4, $22, 0
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addiu $4, $22, 1
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xori $4, $22, 1
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ori $4, $22, 1
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andi $4, $22, 1
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slti $4, $22, 1
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sltiu $4, $22, 1
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addiu $4, $22, 0x8000
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xori $4, $22, 0x8000
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ori $4, $22, 0x8000
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andi $4, $22, 0x8000
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slti $4, $22, 0x8000
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sltiu $4, $22, 0x8000
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addiu $4, $22, 0x7FFF
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xori $4, $22, 0x7FFF
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ori $4, $22, 0x7FFF
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andi $4, $22, 0x7FFF
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slti $4, $22, 0x7FFF
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sltiu $4, $22, 0x7FFF
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mflo $7
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mflo $30
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mfhi $7
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mfhi $30
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mtlo $7
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mtlo $30
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mthi $7
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mthi $30
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mult $6, $7
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mult $18, $20
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multu $6, $7
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multu $18, $20
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div $0, $6, $7
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div $0, $18, $20
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divu $0, $6, $7
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divu $0, $18, $20
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jr $5
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jr $31
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jalr $5
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jalr $20
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bltzal $4, 1f
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bltzal $20, 1f
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bgezal $4, 1f
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bgezal $20, 1f
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bltz $4, 1f
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bltz $20, 1f
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1:
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lb $4, ($5)
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lbu $4, ($5)
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lh $4, ($5)
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lhu $4, ($5)
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lw $4, ($5)
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lb $4, 1($5)
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lbu $4, 1($5)
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lh $4, 1($5)
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lhu $4, 1($5)
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lw $4, 1($5)
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lb $4, -1($5)
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lbu $4, -1($5)
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lh $4, -1($5)
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lhu $4, -1($5)
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lw $4, -1($5)
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lb $4, 0x7FFF($5)
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lbu $4, 0x7FFF($5)
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lh $4, 0x7FFF($5)
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lhu $4, 0x7FFF($5)
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lw $4, 0x7FFF($5)
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lb $4, -0x8000($5)
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lbu $4, -0x8000($5)
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lh $4, -0x8000($5)
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lhu $4, -0x8000($5)
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lw $4, -0x8000($5)
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sb $4, ($5)
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sh $4, ($5)
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sw $4, ($5)
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sb $4, 1($5)
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sh $4, 1($5)
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sw $4, 1($5)
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sb $4, -1($5)
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sh $4, -1($5)
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sw $4, -1($5)
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sb $4, 0x7FFF($5)
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sh $4, 0x7FFF($5)
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sw $4, 0x7FFF($5)
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sb $4, -0x8000($5)
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sh $4, -0x8000($5)
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sw $4, -0x8000($5)
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# MIPS32r2/PSP instructions
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ext $2, $5, 20, 4
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ext $15, $20, 3, 9
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ins $2, $5, 20, 4
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ins $15, $20, 3, 9
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seb $7, $9
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seh $7, $9
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# PSP specific stuff
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# max $4, $28, $15
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# min $4, $28, $15
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# movz $4, $5, $6
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# movn $4, $5, $6
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@ -0,0 +1,121 @@
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#define u32 uint32_t
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#define u8 uint8_t
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#include <stdio.h>
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#include <stdint.h>
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#include "mips_codegen.h"
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int main() {
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u32 buffer[1024];
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u8 *translation_ptr = (u8*)&buffer[0];
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mips_emit_nop();
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mips_emit_nop();
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mips_emit_addu(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_addu(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_subu(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_subu(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_xor(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_xor(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_and(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_and(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_or(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_or(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_nor(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_nor(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_slt(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_slt(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_sltu(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_sltu(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_sllv(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_sllv(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_srlv(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_srlv(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_srav(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_srav(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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mips_emit_rotrv(mips_reg_a0, mips_reg_a1, mips_reg_a2);
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mips_emit_rotrv(mips_reg_sp, mips_reg_ra, mips_reg_s4);
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for (unsigned i = 0; i < 4; i++) {
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mips_emit_sll(mips_reg_a0, mips_reg_a1, (i & 1) + (i >> 1) * 30);
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mips_emit_srl(mips_reg_a0, mips_reg_a1, (i & 1) + (i >> 1) * 30);
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mips_emit_sra(mips_reg_a0, mips_reg_a1, (i & 1) + (i >> 1) * 30);
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mips_emit_rotr(mips_reg_a0, mips_reg_a1, (i & 1) + (i >> 1) * 30);
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}
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mips_emit_lui(mips_reg_a0, 0xFFFF);
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mips_emit_lui(mips_reg_a0, 0x8000);
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mips_emit_lui(mips_reg_a0, 0);
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mips_emit_lui(mips_reg_a0, 1);
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const int imm[] = {-1, 0, 1, 0x8000, 0x7FFF};
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for (unsigned i = 0; i < 5; i++) {
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mips_emit_addiu(mips_reg_a0, mips_reg_s6, imm[i]);
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mips_emit_xori(mips_reg_a0, mips_reg_s6, imm[i]);
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mips_emit_ori(mips_reg_a0, mips_reg_s6, imm[i]);
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mips_emit_andi(mips_reg_a0, mips_reg_s6, imm[i]);
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mips_emit_slti(mips_reg_a0, mips_reg_s6, imm[i]);
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mips_emit_sltiu(mips_reg_a0, mips_reg_s6, imm[i]);
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}
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mips_emit_mflo(mips_reg_a3);
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mips_emit_mflo(mips_reg_fp);
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mips_emit_mfhi(mips_reg_a3);
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mips_emit_mfhi(mips_reg_fp);
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mips_emit_mtlo(mips_reg_a3);
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mips_emit_mtlo(mips_reg_fp);
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mips_emit_mthi(mips_reg_a3);
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mips_emit_mthi(mips_reg_fp);
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mips_emit_mult(mips_reg_a2, mips_reg_a3);
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mips_emit_mult(mips_reg_s2, mips_reg_s4);
|
||||
mips_emit_multu(mips_reg_a2, mips_reg_a3);
|
||||
mips_emit_multu(mips_reg_s2, mips_reg_s4);
|
||||
mips_emit_div(mips_reg_a2, mips_reg_a3);
|
||||
mips_emit_div(mips_reg_s2, mips_reg_s4);
|
||||
mips_emit_divu(mips_reg_a2, mips_reg_a3);
|
||||
mips_emit_divu(mips_reg_s2, mips_reg_s4);
|
||||
|
||||
mips_emit_jr(mips_reg_a1);
|
||||
mips_emit_jr(mips_reg_ra);
|
||||
mips_emit_jalr(mips_reg_a1);
|
||||
mips_emit_jalr(mips_reg_s4);
|
||||
|
||||
mips_emit_bltzal(mips_reg_a0, 5);
|
||||
mips_emit_bltzal(mips_reg_s4, 4);
|
||||
mips_emit_bgezal(mips_reg_a0, 3);
|
||||
mips_emit_bgezal(mips_reg_s4, 2);
|
||||
mips_emit_bltz(mips_reg_a0, 1);
|
||||
mips_emit_bltz(mips_reg_s4, 0);
|
||||
|
||||
const int off[] = {0, 1, -1, 0x7FFF, -0x8000};
|
||||
for (unsigned i = 0; i < 5; i++) {
|
||||
mips_emit_lb(mips_reg_a0, mips_reg_a1, off[i]);
|
||||
mips_emit_lbu(mips_reg_a0, mips_reg_a1, off[i]);
|
||||
mips_emit_lh(mips_reg_a0, mips_reg_a1, off[i]);
|
||||
mips_emit_lhu(mips_reg_a0, mips_reg_a1, off[i]);
|
||||
mips_emit_lw(mips_reg_a0, mips_reg_a1, off[i]);
|
||||
}
|
||||
for (unsigned i = 0; i < 5; i++) {
|
||||
mips_emit_sb(mips_reg_a0, mips_reg_a1, off[i]);
|
||||
mips_emit_sh(mips_reg_a0, mips_reg_a1, off[i]);
|
||||
mips_emit_sw(mips_reg_a0, mips_reg_a1, off[i]);
|
||||
}
|
||||
|
||||
// MIPS32r2/PSP instructions
|
||||
mips_emit_ext(mips_reg_v0, mips_reg_a1, 20, 4);
|
||||
mips_emit_ext(mips_reg_t7, mips_reg_s4, 3, 9);
|
||||
mips_emit_ins(mips_reg_v0, mips_reg_a1, 20, 4);
|
||||
mips_emit_ins(mips_reg_t7, mips_reg_s4, 3, 9);
|
||||
|
||||
mips_emit_seb(mips_reg_a3, mips_reg_t1);
|
||||
mips_emit_seh(mips_reg_a3, mips_reg_t1);
|
||||
|
||||
fwrite(buffer, 1, translation_ptr-(u8*)buffer, stdout);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue