Fix potential MIPS issue on cache alignment
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@ -2536,7 +2536,8 @@ void translate_icache_sync() {
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redo: \
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\
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/* Pad the start of the block to 16 bytes, see "memory tagging" above */ \
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while ((((uintptr_t)ram_translation_ptr) % 16) != block_prologue_size) \
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while (((uintptr_t)(&ram_translation_ptr[block_prologue_size] \
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- ram_translation_cache)) % 16) \
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ram_translation_ptr++; \
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\
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translation_recursion_level++; \
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