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Merge pull request #104 from davidgfnet/master 

Improve and simplify dynarec JIT area.
This commit is contained in:
Autechre 2021-03-12 22:36:33 +01:00 committed by GitHub
parent e178b25425 1e8097ac79
commit 8d60fb2507
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 14 additions and 50 deletions
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15
Makefile
View File

@ -166,12 +166,12 @@ else ifeq ($(platform), qnx)
fpic := -fPIC
SHARED := -shared -Wl,--version-script=link.T
HAVE_MMAP = 1
CPU_ARCH := arm
CC = qcc -Vgcc_ntoarmv7le
AR = qcc -Vgcc_ntoarmv7le
CFLAGS += -D__BLACKBERRY_QNX_
HAVE_DYNAREC := 1
CFLAGS += -DARM -DARM_ARCH -DARM_MEMORY_DYNAREC
# Lightweight PS3 Homebrew SDK
else ifeq ($(platform), psl1ght)
@ -238,10 +238,8 @@ else ifeq ($(platform), rpi3)
TARGET := $(TARGET_NAME)_libretro.so
fpic := -fPIC
SHARED := -shared -Wl,--version-script=link.T -Wl,--no-undefined
CFLAGS += -DARM -DARM_ARCH
CFLAGS += -marm -mcpu=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=hard
CFLAGS += -fomit-frame-pointer -ffast-math
CFLAGS += -DARM_MEMORY_DYNAREC
CXXFLAGS = $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
CPU_ARCH := arm
HAVE_DYNAREC = 1
@ -251,10 +249,8 @@ else ifeq ($(platform), rpi2)
TARGET := $(TARGET_NAME)_libretro.so
fpic := -fPIC
SHARED := -shared -Wl,--version-script=link.T -Wl,--no-undefined
CFLAGS += -DARM -DARM_ARCH
CFLAGS += -marm -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard
CFLAGS += -fomit-frame-pointer -ffast-math
CFLAGS += -DARM_MEMORY_DYNAREC
CXXFLAGS = $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
CPU_ARCH := arm
HAVE_DYNAREC = 1
@ -264,10 +260,9 @@ else ifeq ($(platform), rpi1)
TARGET := $(TARGET_NAME)_libretro.so
fpic := -fPIC
SHARED := -shared -Wl,--version-script=link.T -Wl,--no-undefined
CFLAGS += -DARM11 -DARM_ARCH
CFLAGS += -DARM11
CFLAGS += -marm -mfpu=vfp -mfloat-abi=hard -march=armv6j
CFLAGS += -fomit-frame-pointer -ffast-math
CFLAGS += -DARM_MEMORY_DYNAREC
CXXFLAGS = $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
CPU_ARCH := arm
HAVE_DYNAREC = 1
@ -298,8 +293,6 @@ else ifeq ($(platform), classic_armv7_a7)
BUILTIN_GPU = neon
CPU_ARCH := arm
HAVE_DYNAREC = 1
CFLAGS += -DARM -DARM_ARCH
CFLAGS += -DARM_MEMORY_DYNAREC
ifeq ($(shell echo `$(CC) -dumpversion` "< 4.9" | bc -l), 1)
CFLAGS += -march=armv7-a
else
@ -363,11 +356,9 @@ else ifneq (,$(findstring armv,$(platform)))
CFLAGS += -mfloat-abi=hard
ASFLAGS += -mfloat-abi=hard
endif
CFLAGS += -DARM -DARM_ARCH
# Dynarec works at least in rpi, take a look at issue #11
ifeq (,$(findstring no-dynarec,$(platform)))
HAVE_DYNAREC := 1
CFLAGS += -DARM_MEMORY_DYNAREC
endif
LDFLAGS := -Wl,--no-undefined
@ -429,6 +420,8 @@ endif
ifeq ($(CPU_ARCH), arm)
DEFINES += -DARM_ARCH
else ifeq ($(CPU_ARCH), mips)
DEFINES += -DMIPS_ARCH
else ifeq ($(CPU_ARCH), x86_32)
DEFINES += -DX86_ARCH
endif

23
cpu_threaded.c
View File

@ -53,7 +53,7 @@ u8* bios_translation_cache_ptr;
u8 *rom_translation_ptr = rom_translation_cache;
u8 *ram_translation_ptr = ram_translation_cache;
u8 *bios_translation_ptr = bios_translation_cache;
#elif defined(ARM_MEMORY_DYNAREC)
#else
#ifdef __ANDROID__
// Workaround for 'attempt to map x bytes at offset y'
@ -75,13 +75,6 @@ u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE]
u8 *bios_translation_ptr = bios_translation_cache;
__asm__(".section .text");
#else
u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE];
u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE];
u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE];
u8 *rom_translation_ptr = rom_translation_cache;
u8 *ram_translation_ptr = ram_translation_cache;
u8 *bios_translation_ptr = bios_translation_cache;
#endif
u32 iwram_code_min = 0xFFFFFFFF;
@ -234,19 +227,13 @@ extern u8 bit_count[256];
#define thumb_decode_branch() \
u32 offset = opcode & 0x07FF \
#ifdef PSP
/* Include the right emitter headers */
#if defined(MIPS_ARCH)
#include "psp/mips_emit.h"
#elif defined(ARM_ARCH)
#include "arm/arm_emit.h"
#else
#include "x86/x86_emit.h"
#endif
/* Cache invalidation */
@ -258,7 +245,7 @@ extern u8 bit_count[256];
}
#elif defined(VITA)
void platform_cache_sync(void *baseaddr, void *endptr) {
sceKernelSyncVMDomain(baseaddr, ((char*)endptr) - ((char*)baseaddr) + 64);
sceKernelSyncVMDomain(sceBlock, baseaddr, ((char*)endptr) - ((char*)baseaddr) + 64);
}
#elif defined(_3DS)
#include "3ds/3ds_utils.h"
@ -271,7 +258,7 @@ extern u8 bit_count[256];
}
#elif defined(MIPS_ARCH)
void platform_cache_sync(void *baseaddr, void *endptr) {
icache_region_sync(baseaddr, ((char*)endptr) - ((char*)baseaddr));
__builtin___clear_cache(baseaddr, endptr);
}
#else
/* x86 CPUs have icache consistency checks */

2
jni/Android.mk
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@ -9,7 +9,7 @@ HAVE_DYNAREC :=
COREFLAGS := -DINLINE=inline -D__LIBRETRO__ -DFRONTEND_SUPPORTS_RGB565
ifeq ($(TARGET_ARCH),arm)
COREFLAGS += -DARM_ARCH -DARM_MEMORY_DYNAREC
COREFLAGS += -DARM_ARCH
CPU_ARCH := arm
HAVE_DYNAREC := 1
else ifeq ($(TARGET_ARCH),x86)

18
psp/mips_stub.S
View File

@ -2808,24 +2808,8 @@ execute_arm_translate:
jr $2 # jump to return
nop
# This is only to be used with MIPS32
# $4: start location
# $5: length
icache_region_sync:
ins $4, $0, 0, 6 # align to 64 bytes
addiu $2, $5, 63 # align up to 64 bytes
srl $2, $2, 6 # divide by 64
1:
synci ($4) # sync caches
addiu $2, $2, -1 # next loop iteration
bne $2, $0, 1b # loop
addiu $4, $4, 64 # go to next cache line (delay slot)
jr $ra # return
nop
.data:
memory_map_read:
.space 0x8000