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Merge pull request #91 from davidgfnet/master 

Fix ARM dynarec
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Autechre 2021-02-10 10:35:56 +01:00 committed by GitHub
parent f70d8534a1 2c6026cfe5
commit 6254bbb1d2
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 4 additions and 10 deletions
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4
arm/arm_emit.h
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@ -174,7 +174,7 @@ s32 arm_register_allocation[] =
reg_x4, /* GBA r12 */ reg_x4, /* GBA r12 */
mem_reg, /* GBA r13 */ mem_reg, /* GBA r13 */
reg_x5, /* GBA r14 */ reg_x5, /* GBA r14 */
reg_a0 /* GBA r15 */ reg_a0, /* GBA r15 */
mem_reg, mem_reg,
mem_reg, mem_reg,
@ -211,7 +211,7 @@ s32 thumb_register_allocation[] =
mem_reg, /* GBA r12 */ mem_reg, /* GBA r12 */
mem_reg, /* GBA r13 */ mem_reg, /* GBA r13 */
mem_reg, /* GBA r14 */ mem_reg, /* GBA r14 */
reg_a0 /* GBA r15 */ reg_a0, /* GBA r15 */
mem_reg, mem_reg,
mem_reg, mem_reg,

10
cpu_threaded.c
View File

@ -272,17 +272,11 @@ extern u8 bit_count[256];
#define invalidate_icache_region(addr, size) (void)0 #define invalidate_icache_region(addr, size) (void)0
#elif defined(ARM_ARCH) #elif defined(ARM_ARCH)
static int sys_cacheflush(void *addr, unsigned long size) static void sys_cacheflush(void *addr, unsigned long size)
{ {
void *start = (void*)addr; void *start = (void*)addr;
void *end = (void*)(char *)addr + size; void *end = (void*)(char *)addr + size;
__clear_cache(start, end);
register const unsigned char *r0 asm("r0") = start;
register const unsigned char *r1 asm("r1") = end;
register const int r2 asm("r2") = 0;
register const int r7 asm("r7") = 0xf0002;
asm volatile ("svc 0x0" :: "r" (r0), "r" (r1), "r" (r2), "r" (r7));
return -1;
} }
#define translate_invalidate_dcache_one(which) \ #define translate_invalidate_dcache_one(which) \