4f3c9a5e58
gpsp doesn't differentiate between USER and SYSTEM mode, most likely cause it is not that important for most games. This implements the modes correctly and adds checks for privileged operations. Still some bugs/hacks but it mostly fixes CPSR/SPSR reads/writes. To implement PSR writes we are using a more refined masks and force mode bit num. 4 to always be one. Reserved bits are forced to zero (this needs to be validated on a real device).
773 lines
33 KiB
ArmAsm
773 lines
33 KiB
ArmAsm
# gameplaySP
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#
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# Copyright (C) 2021 David Guillen Fandos <david@davidgf.net>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#include "../gpsp_config.h"
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#define defsymbl(symbol) \
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.align 2; \
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.type symbol, %function ;\
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.global symbol ; \
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.global _##symbol ; \
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symbol: \
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_##symbol:
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.text
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.align 2
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#define REG_R0 (0 * 4)
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#define REG_R1 (1 * 4)
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#define REG_R2 (2 * 4)
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#define REG_R3 (3 * 4)
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#define REG_R4 (4 * 4)
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#define REG_R5 (5 * 4)
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#define REG_R6 (6 * 4)
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#define REG_R7 (7 * 4)
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#define REG_R8 (8 * 4)
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#define REG_R9 (9 * 4)
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#define REG_R10 (10 * 4)
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#define REG_R11 (11 * 4)
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#define REG_R12 (12 * 4)
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#define REG_R13 (13 * 4)
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#define REG_R14 (14 * 4)
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#define REG_SP (13 * 4)
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#define REG_LR (14 * 4)
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#define REG_PC (15 * 4)
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#define REG_CPSR (16 * 4)
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#define CPU_MODE (17 * 4)
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#define CPU_HALT_STATE (18 * 4)
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#define REG_BUS_VALUE (19 * 4)
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#define REG_N_FLAG (20 * 4)
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#define REG_Z_FLAG (21 * 4)
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#define REG_C_FLAG (22 * 4)
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#define REG_V_FLAG (23 * 4)
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#define CHANGED_PC_STATUS (24 * 4)
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#define COMPLETED_FRAME (25 * 4)
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#define OAM_UPDATED (26 * 4)
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#define REG_SAVE (27 * 4)
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#define REG_SAVE2 (28 * 4)
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#define REG_SAVE3 (29 * 4)
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#define REG_SAVE4 (30 * 4)
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#define REG_SAVE5 (31 * 4)
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#define reg_base x20
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#define reg_cycles w21
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#define reg_c_flag w22
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#define reg_v_flag w23
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#define reg_z_flag w24
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#define reg_n_flag w25
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// Memory offsets from reg_base to the different buffers
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#define RDMAP_OFF -0xB9000 // 8K pointers (64KB)
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#define IWRAM_OFF -0xA9000 // 32KB (double for shadow)
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#define VRAM_OFF -0x99000 // 96KB
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#define EWRAM_OFF -0x81000 // 256KB (double for shadow)
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#define MEM_TBL_OFF -0x1000 // Some space for the tables
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#define SPSR_RAM_OFF 0x100
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#define REGMODE_RAM_OFF 0x118
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#define OAM_RAM_OFF 0x200
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#define PAL_RAM_OFF 0x600
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#define IOREG_OFF 0xA00
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#define PALCNV_RAM_OFF 0xE00
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// Used for SWI handling
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#define MODE_SUPERVISOR 0x13
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#define SUPERVISOR_SPSR (SPSR_RAM_OFF + 3*4) // spsr[3]
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#define SUPERVISOR_LR (REGMODE_RAM_OFF + (3 * (7 * 4)) + (6 * 4)) // reg_mode[3][6]
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// Stores and restores registers to their register storage in RAM
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#define load_registers() ;\
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ldp w6, w7, [reg_base, #0] ;\
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ldp w8, w9, [reg_base, #8] ;\
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ldp w10, w11, [reg_base, #16] ;\
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ldp w12, w13, [reg_base, #24] ;\
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ldp w14, w15, [reg_base, #32] ;\
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ldp w16, w17, [reg_base, #40] ;\
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ldp w26, w27, [reg_base, #48] ;\
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ldr w28, [reg_base, #56] ;\
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#define store_registers() ;\
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stp w6, w7, [reg_base, #0] ;\
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stp w8, w9, [reg_base, #8] ;\
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stp w10, w11, [reg_base, #16] ;\
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stp w12, w13, [reg_base, #24] ;\
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stp w14, w15, [reg_base, #32] ;\
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stp w16, w17, [reg_base, #40] ;\
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stp w26, w27, [reg_base, #48] ;\
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str w28, [reg_base, #56] ;\
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// Extracts flags from CPSR into the cache flag registers
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#define extract_flags_reg(tmpreg) ;\
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ubfx reg_n_flag, tmpreg, #31, #1 ;\
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ubfx reg_z_flag, tmpreg, #30, #1 ;\
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ubfx reg_c_flag, tmpreg, #29, #1 ;\
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ubfx reg_v_flag, tmpreg, #28, #1 ;\
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#define extract_flags(tmpreg) ;\
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ldr tmpreg, [reg_base, #REG_CPSR] ;\
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extract_flags_reg(tmpreg) ;\
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// Collects cache flag bits and consolidates them to the CPSR reg
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#define consolidate_flags(tmpreg) ;\
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ldr tmpreg, [reg_base, #REG_CPSR] ;\
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bfi tmpreg, reg_n_flag, #31, #1 ;\
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bfi tmpreg, reg_z_flag, #30, #1 ;\
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bfi tmpreg, reg_c_flag, #29, #1 ;\
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bfi tmpreg, reg_v_flag, #28, #1 ;\
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str tmpreg, [reg_base, #REG_CPSR] ;\
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// Update the GBA hardware (video, sound, input, etc)
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// w0: current PC
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defsymbl(a64_update_gba)
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str w0, [reg_base, #REG_PC] // update the PC value
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str lr, [reg_base, #REG_SAVE] // Save LR for later if needed
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consolidate_flags(w0) // update the CPSR
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store_registers() // save out registers
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mov w0, reg_cycles // load remaining cycles
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bl update_gba // update GBA state
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ldr w1, [reg_base, #COMPLETED_FRAME] // return to main if new frame
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cbnz w1, return_to_main
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// Resume execution (perhaps from a new PC)
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mov reg_cycles, w0 // load new cycle count
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extract_flags(w2) // reload flag cache bits
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ldr w0, [reg_base, #CHANGED_PC_STATUS] // see if PC has change
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cbnz w0, 1f // go start from new PC
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ldr lr, [reg_base, #REG_SAVE] // Restore return point
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load_registers() // reload registers
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ret // resume execution, no PC change
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1: // Resume from new PC
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ldr w0, [reg_base, #REG_PC] // load new PC
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tbnz w2, #5, 2f // CPSR.T means in thumb mode
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bl block_lookup_address_arm
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load_registers() // reload registers
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br x0 // jump to new ARM block
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2:
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bl block_lookup_address_thumb
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load_registers() // reload registers
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br x0 // jump to new Thumb block
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.size a64_update_gba, .-a64_update_gba
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// Cheat hooks for master function
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// This is called whenever PC == cheats-master-function
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// Just calls the C function to process cheats
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defsymbl(a64_cheat_hook)
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store_registers()
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str lr, [reg_base, #REG_SAVE]
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bl process_cheats
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ldr lr, [reg_base, #REG_SAVE]
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load_registers()
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ret
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// These are b stubs for performing indirect branches. They are not
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// linked to and don't return, instead they link elsewhere.
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// Input:
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// r0: PC to branch to
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defsymbl(a64_indirect_branch_arm)
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store_registers()
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bl block_lookup_address_arm
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load_registers()
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br x0
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defsymbl(a64_indirect_branch_thumb)
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store_registers()
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bl block_lookup_address_thumb
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load_registers()
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br x0
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defsymbl(a64_indirect_branch_dual)
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store_registers()
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bl block_lookup_address_dual
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load_registers()
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br x0
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// Read CPSR and SPSR values
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defsymbl(execute_read_cpsr)
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consolidate_flags(w0) // Consolidate on ret value
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ret
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defsymbl(execute_read_spsr)
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ldr w1, [reg_base, #CPU_MODE] // read cpu mode to w1
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and w1, w1, #0xF // Like REG_SPSR() macro
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add x0, reg_base, #SPSR_RAM_OFF // ptr to spsr table
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ldr w0, [x0, x1, lsl #2] // Read actual value from table
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ret
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// Update the cpsr.
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// Input:
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// w0: new cpsr value
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// w1: current PC
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// w2: store bitmask (user-mode)
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// w3: store bitmask (privileged mode)
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defsymbl(execute_store_cpsr)
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ldr w4, [reg_base, #CPU_MODE] // w4 = cpu_mode
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tst x4, #0x10 // Bit 4 is set on privileged modes
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csel x2, x2, x3, eq // Select the correct mask
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ldr w4, [reg_base, #REG_CPSR] // read current CPSR
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and w3, w0, w2 // reg_flags = new_cpsr & store_mask
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bic w4, w4, w2 // current_cpsr & ~store_mask
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orr w0, w3, w4 // w2 = final CPSR value
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extract_flags_reg(w0) // Update cached flags too
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str lr, [reg_base, #REG_SAVE]
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store_registers()
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bl execute_store_cpsr_body // Do the remaining work in C mode
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cbnz w0, 1f // If PC has changed due to this
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ldr lr, [reg_base, #REG_SAVE] // Resume execution where we left it
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load_registers()
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ret
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1:
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// Returned value contains the PC, resume execution there
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bl block_lookup_address_arm
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load_registers()
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br x0 // Resume in the returned block
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.size execute_store_cpsr, .-execute_store_cpsr
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// Write to SPSR
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// w0: new SPSR value
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// w1: store mask
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defsymbl(execute_store_spsr)
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ldr w2, [reg_base, #CPU_MODE] // read cpu mode to w1
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and w2, w2, #0xF // Like REG_SPSR() macro
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add x2, reg_base, x2, lsl #2 // calculate table offset
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ldr w3, [x2, #SPSR_RAM_OFF] // Read actual value from trable
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and w0, w0, w1 // new-spsr & mask
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bic w3, w3, w1 // old-spsr & ~mask
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orr w0, w0, w3 // final spsr value
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str w0, [x2, #SPSR_RAM_OFF] // Store new SPSR
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ret
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.size execute_store_spsr, .-execute_store_spsr
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// Restore the cpsr from the mode spsr and mode shift.
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// Input:
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// r0: current pc
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defsymbl(execute_spsr_restore)
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ldr w1, [reg_base, #CPU_MODE] // w1 = cpu_mode
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and w1, w1, 0xF // Fold user and system modes
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cbz w1, 1f // Ignore if in user or system mode
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lsl w2, w1, #2 // We access 32 bit words
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add w2, w2, #SPSR_RAM_OFF
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ldr w3, [reg_base, x2] // w3 = spsr[cpu_mode]
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str w3, [reg_base, #REG_CPSR] // update CPSR with SPSR value
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extract_flags_reg(w3) // update cached flag values
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// This function call will pass r0 (address) and return it.
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str lr, [reg_base, #REG_SAVE]
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store_registers() // save ARM registers
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bl execute_spsr_restore_body
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ldr lr, [reg_base, #REG_SAVE]
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load_registers()
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1:
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ret
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.size execute_spsr_restore, .-execute_spsr_restore
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// Setup the mode transition work for calling an SWI.
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// Input:
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// r0: current pc
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defsymbl(execute_swi)
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str lr, [reg_base, #REG_SAVE]
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str w0, [reg_base, #SUPERVISOR_LR] // Store next PC into supervisor LR
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consolidate_flags(w1) // Calculate current CPSR flags
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str w1, [reg_base, #SUPERVISOR_SPSR] // Store them in the SPSR
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bic w1, w1, #0x3F // Clear mode bits
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mov w2, #(0x13 | 0x80) // Set supervisor mode bits
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orr w1, w1, w2
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str w1, [reg_base, #REG_CPSR] // Update CPSR with new value
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store_registers()
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mov w0, #MODE_SUPERVISOR
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bl set_cpu_mode // Set supervisor mode
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ldr w0, =0xe3a02004
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str w0, [reg_base, REG_BUS_VALUE]
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ldr lr, [reg_base, #REG_SAVE]
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load_registers()
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ret
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.size execute_swi, .-execute_swi
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defsymbl(execute_arm_translate_internal)
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// save registers that will be clobbered
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sub sp, sp, #96
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stp x19, x20, [sp, #0]
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stp x21, x22, [sp, #16]
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stp x23, x24, [sp, #32]
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stp x25, x26, [sp, #48]
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stp x27, x28, [sp, #64]
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stp x29, x30, [sp, #80]
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mov reg_cycles, w0 // load cycle counter
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mov reg_base, x1 // init base_reg
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// Check whether the CPU is sleeping already, we should just wait for IRQs
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ldr w1, [reg_base, #CPU_HALT_STATE]
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cmp w1, #0
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bne alert_loop
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ldr w0, [reg_base, #REG_PC] // r0 = current pc
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ldr w1, [reg_base, #REG_CPSR] // r1 = flags
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tst w1, #0x20 // see if Thumb bit is set
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extract_flags(w2) // load flags
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bne 1f // if so lookup thumb
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bl block_lookup_address_arm
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load_registers()
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br x0 // jump to first ARM block
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1:
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bl block_lookup_address_thumb
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load_registers()
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br x0 // jump to first Thumb block
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// Epilogue to return to the main thread (whatever called execute_arm_translate)
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return_to_main:
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// restore the saved regs and return
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ldp x19, x20, [sp, #0]
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ldp x21, x22, [sp, #16]
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ldp x23, x24, [sp, #32]
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ldp x25, x26, [sp, #48]
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ldp x27, x28, [sp, #64]
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ldp x29, x30, [sp, #80]
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add sp, sp, #96
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ret
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// Memory read stub routines
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#define execute_load_builder(load_type, ldop, ldmask, tblidx, ldfn) ;\
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;\
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defsymbl(execute_load_##load_type) ;\
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tst w0, #(0xf0000000 | ldmask) ;\
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lsr w3, w0, #24 ;\
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csinc w3, wzr, w3, ne ;\
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add x4, reg_base, (MEM_TBL_OFF + tblidx*136) ;\
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ldr x3, [x4, x3, lsl #3] ;\
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br x3 ;\
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;\
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ld_bios_##load_type: /* BIOS area, need to verify PC */;\
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lsr w3, w1, #24 /* Are we running the BIOS */;\
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cbnz w3, ld_slow_##load_type ;\
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and w0, w0, #(0x7fff) /* BIOS only 16 KB */;\
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add x3, reg_base, #(RDMAP_OFF) ;\
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ldr x3, [x3] /* x3 = bios mem buffer */;\
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ldop w0, [x3, x0] /* load actual value */;\
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ret ;\
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;\
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ld_ewram_##load_type: /* EWRAM area */;\
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and w0, w0, #(0x3ffff) ;\
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add x3, reg_base, #EWRAM_OFF ;\
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ldop w0, [x3, x0] ;\
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ret ;\
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;\
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ld_iwram_##load_type: /* IWRAM area */;\
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and w0, w0, #(0x7fff) ;\
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add x3, reg_base, #(IWRAM_OFF+0x8000) ;\
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ldop w0, [x3, x0] ;\
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ret ;\
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;\
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ld_ioram_##load_type: /* I/O RAM area */;\
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and w0, w0, #(0x3ff) ;\
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add x3, reg_base, #(IOREG_OFF) ;\
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ldop w0, [x3, x0] ;\
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ret ;\
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;\
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ld_palram_##load_type: /* PAL RAM area */;\
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and w0, w0, #(0x3ff) ;\
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add x3, reg_base, #(PAL_RAM_OFF) ;\
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ldop w0, [x3, x0] ;\
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ret ;\
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;\
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ld_oamram_##load_type: /* OAM RAM area */;\
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and w0, w0, #(0x3ff) ;\
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add x3, reg_base, #(OAM_RAM_OFF) ;\
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ldop w0, [x3, x0] ;\
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ret ;\
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;\
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ld_rdmap_##load_type: ;\
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lsr w4, w0, #15 /* Each block is 32KB */;\
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add x3, reg_base, #(RDMAP_OFF) ;\
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ldr x4, [x3, x4, lsl #3] /* x4 = table pointer */;\
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and w0, w0, #(0x7fff) /* 32KB pages */;\
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ldop w0, [x4, x0] /* load actual value */;\
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ret ;\
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;\
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ld_slow_##load_type: /* Slow C path */;\
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str w1, [reg_base, #REG_PC] /* write out PC */;\
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str lr, [reg_base, #REG_SAVE] /* Save LR */;\
|
|
store_registers() ;\
|
|
bl ldfn ;\
|
|
ldr lr, [reg_base, #REG_SAVE] ;\
|
|
load_registers() ;\
|
|
ret ;\
|
|
.size execute_load_##load_type, .-execute_load_##load_type
|
|
|
|
#define load_lookup_table(load_type, aload_type) ;\
|
|
.quad ld_slow_##aload_type /* -1: Unaligned/Bad access */;\
|
|
.quad ld_bios_##aload_type /* 0x00: BIOS */;\
|
|
.quad ld_slow_##aload_type /* 0x01: Open bus */;\
|
|
.quad ld_ewram_##load_type /* 0x02: ewram */;\
|
|
.quad ld_iwram_##load_type /* 0x03: iwram */;\
|
|
.quad ld_ioram_##load_type /* 0x04: I/O regs */;\
|
|
.quad ld_palram_##load_type /* 0x05: palette RAM */;\
|
|
.quad ld_rdmap_##load_type /* 0x06: vram */;\
|
|
.quad ld_oamram_##load_type /* 0x07: oam ram */;\
|
|
.quad ld_rdmap_##load_type /* 0x08: gamepak: ignore */;\
|
|
.quad ld_rdmap_##load_type /* 0x09: gamepak: ignore */;\
|
|
.quad ld_rdmap_##load_type /* 0x0A: gamepak: ignore */;\
|
|
.quad ld_rdmap_##load_type /* 0x0B: gamepak: ignore */;\
|
|
.quad ld_rdmap_##load_type /* 0x0C: gamepak: ignore */;\
|
|
.quad ld_slow_##aload_type /* 0x0D: EEPROM */;\
|
|
.quad ld_slow_##aload_type /* 0x0E: backup */;\
|
|
.quad ld_slow_##aload_type /* 0x0F: ignore */;\
|
|
|
|
// Aligned load is a bit special
|
|
defsymbl(execute_aligned_load32)
|
|
tst w0, #(0xf0000000)
|
|
lsr w3, w0, #24
|
|
csinc w3, wzr, w3, ne
|
|
add x4, reg_base, (MEM_TBL_OFF + 5*136)
|
|
ldr x3, [x4, x3, lsl #3]
|
|
br x3
|
|
ld_slow_aligned_u32: // Slow C path for multiple loads
|
|
str lr, [reg_base, #REG_SAVE] // Save LR
|
|
store_registers()
|
|
bl read_memory32
|
|
ldr lr, [reg_base, #REG_SAVE]
|
|
load_registers()
|
|
ret
|
|
ld_bios_aligned_u32:
|
|
and w0, w0, #(0x7fff) // Do not verify PC on purpose
|
|
add x3, reg_base, #(RDMAP_OFF)
|
|
ldr x3, [x3]
|
|
ldr w0, [x3, x0]
|
|
ret
|
|
|
|
|
|
execute_load_builder( u8, ldrb, 0, 0, read_memory8)
|
|
execute_load_builder( s8, ldrsb, 0, 1, read_memory8s)
|
|
execute_load_builder(u16, ldrh, 1, 2, read_memory16)
|
|
execute_load_builder(s16, ldrsh, 1, 3, read_memory16s)
|
|
execute_load_builder(u32, ldr, 3, 4, read_memory32)
|
|
|
|
|
|
// Prepares for a external store (calls C code)
|
|
#define store_align_8() and w1, w1, #0xff
|
|
#define store_align_16() and w1, w1, #0xffff; bic w0, w0, #1
|
|
#define store_align_32() bic w0, w0, #3
|
|
|
|
// Write out to memory.
|
|
|
|
// Input:
|
|
// w0: address
|
|
// w1: value
|
|
// w2: PC value
|
|
|
|
#define execute_store_builder(store_type, str_op, str_op16, load_op, \
|
|
stmask, stmask16, tblidx) ;\
|
|
;\
|
|
defsymbl(execute_store_u##store_type) ;\
|
|
lsr w4, w0, #28 ;\
|
|
lsr w3, w0, #24 ;\
|
|
cbnz w4, ext_store_u##store_type ;\
|
|
add x4, reg_base, (MEM_TBL_OFF + 816 + tblidx*128) ;\
|
|
ldr x3, [x4, x3, lsl #3] ;\
|
|
br x3 ;\
|
|
;\
|
|
ext_store_u##store_type: ;\
|
|
ext_store_u##store_type##_safe: ;\
|
|
str w2, [reg_base, #REG_PC] /* write out PC */;\
|
|
str lr, [reg_base, #REG_SAVE] /* Preserve LR */;\
|
|
store_align_##store_type() ;\
|
|
store_registers() ;\
|
|
bl write_memory##store_type ;\
|
|
cbnz w0, write_epilogue /* handle additional write stuff */;\
|
|
ldr lr, [reg_base, #REG_SAVE] ;\
|
|
load_registers() ;\
|
|
ret /* resume if no side effects */;\
|
|
;\
|
|
ext_store_iwram_u##store_type: ;\
|
|
and w0, w0, #(0x7fff & ~stmask) /* Mask to mirror memory (+align)*/;\
|
|
add x3, reg_base, #(IWRAM_OFF+0x8000) /* x3 = iwram base */;\
|
|
str_op w1, [x0, x3] /* store data */;\
|
|
sub x3, x3, #0x8000 /* x3 = iwram smc base */;\
|
|
load_op w1, [x0, x3] /* w1 = SMC sentinel */;\
|
|
cbnz w1, 3f /* Check value, should be zero */;\
|
|
ret /* return */;\
|
|
;\
|
|
ext_store_ewram_u##store_type: ;\
|
|
and w0, w0, #(0x3ffff & ~stmask) /* Mask to mirror memory (+align)*/;\
|
|
add x3, reg_base, #EWRAM_OFF /* x3 = ewram base */;\
|
|
str_op w1, [x0, x3] /* store data */;\
|
|
add x3, x3, #0x40000 /* x3 = ewram smc base */;\
|
|
load_op w1, [x0, x3] /* w1 = SMC sentinel */;\
|
|
cbnz w1, 3f /* Check value, should be zero */;\
|
|
ret /* return */;\
|
|
;\
|
|
ext_store_vram_u##store_type: ;\
|
|
ext_store_vram_u##store_type##_safe: ;\
|
|
and w0, w0, #(0x1ffff & ~stmask16) /* Mask to mirror memory (+align)*/;\
|
|
sub w3, w0, #0x8000 /* Mirrored addr for last bank */;\
|
|
cmp w0, #0x18000 /* Check if exceeds 96KB */;\
|
|
csel w0, w3, w0, cs /* If it does, pick the mirror */;\
|
|
add x3, reg_base, #VRAM_OFF /* x3 = ewram base */;\
|
|
str_op16 w1, [x0, x3] /* store data */;\
|
|
ret /* return */;\
|
|
;\
|
|
ext_store_oam_ram_u##store_type: ;\
|
|
ext_store_oam_ram_u##store_type##_safe: ;\
|
|
and w0, w0, #(0x3ff & ~stmask16) /* Mask to mirror memory (+align)*/;\
|
|
add x3, reg_base, #OAM_RAM_OFF /* x3 = oam ram base */;\
|
|
str_op16 w1, [x0, x3] /* store data */;\
|
|
str w29, [reg_base, #OAM_UPDATED] /* write non zero to signal */;\
|
|
ret /* return */;\
|
|
;\
|
|
ext_store_ioreg_u##store_type: ;\
|
|
str w2, [reg_base, #REG_PC] /* write out PC */;\
|
|
str lr, [reg_base, #REG_SAVE] /* Preserve LR */;\
|
|
and w0, w0, #(0x3ff & ~stmask) ;\
|
|
store_registers() ;\
|
|
bl write_io_register##store_type ;\
|
|
cbnz w0, write_epilogue /* handle additional write stuff */;\
|
|
ldr lr, [reg_base, #REG_SAVE] ;\
|
|
load_registers() ;\
|
|
ret /* resume if no side effects */;\
|
|
;\
|
|
3: ;\
|
|
str w2, [reg_base, #REG_PC] /* write out PC */;\
|
|
store_registers() /* store registers */;\
|
|
consolidate_flags(w1) ;\
|
|
b smc_write /* perform smc write */;\
|
|
.size execute_store_u##store_type, .-execute_store_u##store_type
|
|
|
|
// for ignored areas, just return
|
|
ext_store_ignore:
|
|
ret // return
|
|
|
|
#define store_lookup_table(store_type) ;\
|
|
.quad ext_store_ignore /* 0x00: BIOS, ignore */;\
|
|
.quad ext_store_ignore /* 0x01: ignore */;\
|
|
.quad ext_store_ewram_u##store_type /* 0x02: ewram */;\
|
|
.quad ext_store_iwram_u##store_type /* 0x03: iwram */;\
|
|
.quad ext_store_ioreg_u##store_type /* 0x04: I/O regs */;\
|
|
.quad ext_store_palette_u##store_type /* 0x05: palette RAM */;\
|
|
.quad ext_store_vram_u##store_type /* 0x06: vram */;\
|
|
.quad ext_store_oam_ram_u##store_type /* 0x07: oam ram */;\
|
|
.quad ext_store_u##store_type /* 0x08: gamepak: ignore */;\
|
|
.quad ext_store_u##store_type /* 0x09: gamepak: ignore */;\
|
|
.quad ext_store_u##store_type /* 0x0A: gamepak: ignore */;\
|
|
.quad ext_store_u##store_type /* 0x0B: gamepak: ignore */;\
|
|
.quad ext_store_u##store_type /* 0x0C: gamepak: ignore */;\
|
|
.quad ext_store_u##store_type /* 0x0D: EEPROM */;\
|
|
.quad ext_store_u##store_type /* 0x0E: backup */;\
|
|
.quad ext_store_ignore /* 0x0F: ignore */;\
|
|
|
|
execute_store_builder(8, strb, strh, ldrb, 0, 1, 0)
|
|
execute_store_builder(16, strh, strh, ldrh, 1, 1, 1)
|
|
execute_store_builder(32, str, str, ldr, 3, 3, 2)
|
|
|
|
// Palette writes are special since they are converted on the fly for speed
|
|
|
|
ext_store_palette_u8:
|
|
bfi w1, w1, #8, #24 // Duplicate the byte
|
|
ext_store_palette_u16:
|
|
and w0, w0, #(0x3fe)
|
|
add x3, reg_base, #(PAL_RAM_OFF)
|
|
strh w1, [x3, x0]
|
|
|
|
ubfx w2, w1, #10, #5 // Extract blue to red
|
|
bfi w2, w1, #11, #5 // Move red to blue
|
|
and w1, w1, #0x03E0 // Extract green component
|
|
orr w1, w2, w1, lsl #1 // Merge the three components
|
|
|
|
add x3, reg_base, #(PALCNV_RAM_OFF)
|
|
strh w1, [x3, x0]
|
|
ret
|
|
|
|
ext_store_palette_u32_safe:
|
|
ext_store_palette_u32:
|
|
and w0, w0, #(0x3fc)
|
|
add x3, reg_base, #(PAL_RAM_OFF)
|
|
str w1, [x3, x0]
|
|
|
|
and w2, w1, #0x7C007C00 // Get blue components
|
|
and w3, w1, #0x001F001F // Get red components
|
|
lsr w2, w2, #10 // Place blue in the final register
|
|
orr w2, w2, w3, lsl #11 // Merge red
|
|
and w3, w1, #0x03E003E0 // Get green component
|
|
orr w1, w2, w3, lsl #1 // Merge green
|
|
|
|
add x3, reg_base, #(PALCNV_RAM_OFF)
|
|
str w1, [x3, x0]
|
|
ret
|
|
|
|
// This is a store that is executed in a strm case (so no SMC checks in-between)
|
|
|
|
defsymbl(execute_aligned_store32)
|
|
lsr w4, w0, #28
|
|
lsr w3, w0, #24
|
|
cbnz w4, ext_store_u32
|
|
add x4, reg_base, MEM_TBL_OFF + 816 + 3*128
|
|
ldr x3, [x4, x3, lsl #3]
|
|
br x3
|
|
ext_store_iwram_u32_safe:
|
|
and w0, w0, #(0x7fff) // Mask to mirror memory (no need to align!)
|
|
add x3, reg_base, #(IWRAM_OFF+0x8000) // x3 = iwram base
|
|
str w1, [x0, x3] // store data
|
|
ret // Return
|
|
ext_store_ewram_u32_safe:
|
|
and w0, w0, #(0x3ffff) // Mask to mirror memory (no need to align!)
|
|
add x3, reg_base, #(EWRAM_OFF) // x3 = ewram base
|
|
str w1, [x0, x3] // store data
|
|
ret // Return
|
|
ext_store_ioreg_u32_safe:
|
|
str lr, [reg_base, #REG_SAVE]
|
|
and w0, w0, #(0x3fc)
|
|
store_registers()
|
|
bl write_io_register32
|
|
cbnz w0, write_epilogue
|
|
ldr lr, [reg_base, #REG_SAVE]
|
|
load_registers()
|
|
ret
|
|
.size execute_aligned_store32, .-execute_aligned_store32
|
|
|
|
// This is called whenever an external store with side effects was performed
|
|
write_epilogue:
|
|
consolidate_flags(w1) // update the CPSR before update
|
|
|
|
cmp w0, #2 // see if the alert is due to SMC
|
|
beq smc_write // if so, goto SMC handler
|
|
|
|
alert_loop:
|
|
mov w0, reg_cycles // load remaining cycles
|
|
bl update_gba // update GBA until CPU isn't halted
|
|
mov reg_cycles, w0 // load new cycle count
|
|
|
|
ldr w1, [reg_base, #COMPLETED_FRAME] // Check whether a frame was completed
|
|
cbnz w1, return_to_main // and return to caller function.
|
|
|
|
ldr w1, [reg_base, #CPU_HALT_STATE] // Check whether the CPU is halted
|
|
cbnz w1, alert_loop // and keep looping until it is
|
|
|
|
ldr w0, [reg_base, #REG_PC] // load new PC
|
|
b lookup_pc // Resume execution at that PC
|
|
|
|
|
|
smc_write:
|
|
bl flush_translation_cache_ram
|
|
ldr w0, [reg_base, #REG_PC] // load "current new" PC
|
|
|
|
// Resume execution at PC (at w0)
|
|
lookup_pc:
|
|
ldr w1, [reg_base, #REG_CPSR] // w1 = flags
|
|
extract_flags_reg(w1)
|
|
tbnz w1, #5, 2f // see if Thumb bit is set
|
|
|
|
// Lookup and jump to the right mode block
|
|
bl block_lookup_address_arm
|
|
load_registers()
|
|
br x0
|
|
2:
|
|
bl block_lookup_address_thumb
|
|
load_registers()
|
|
br x0
|
|
|
|
.data
|
|
.align 4
|
|
defsymbl(ldst_handler_functions)
|
|
load_lookup_table(u8, u8)
|
|
load_lookup_table(s8, s8)
|
|
load_lookup_table(u16, u16)
|
|
load_lookup_table(s16, s16)
|
|
load_lookup_table(u32, u32)
|
|
load_lookup_table(u32, aligned_u32)
|
|
store_lookup_table(8)
|
|
store_lookup_table(16)
|
|
store_lookup_table(32)
|
|
store_lookup_table(32_safe)
|
|
|
|
.bss
|
|
.align 4
|
|
|
|
defsymbl(memory_map_read)
|
|
.space 0x10000
|
|
defsymbl(iwram)
|
|
.space 0x10000
|
|
defsymbl(vram)
|
|
.space 0x18000
|
|
defsymbl(ewram)
|
|
.space 0x80000
|
|
defsymbl(ldst_lookup_tables)
|
|
.space 4096
|
|
defsymbl(reg)
|
|
.space 0x100
|
|
defsymbl(spsr)
|
|
.space 24
|
|
defsymbl(reg_mode)
|
|
.space 196
|
|
.space 36 // Padding
|
|
defsymbl(oam_ram)
|
|
.space 0x400
|
|
defsymbl(palette_ram)
|
|
.space 0x400
|
|
defsymbl(io_registers)
|
|
.space 0x400
|
|
defsymbl(palette_ram_converted)
|
|
.space 0x400
|
|
|
|
|