187 lines
5.3 KiB
C
187 lines
5.3 KiB
C
/* gameplaySP
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*
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* Copyright (C) 2006 Exophase <exophase@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CPU_H
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#define CPU_H
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#include <stdbool.h>
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#include "gpsp_config.h"
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// System mode and user mode are represented as the same here
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typedef u32 cpu_mode_type;
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// Bit 4 indicates privilege level
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#define MODE_USER 0x00 // Non-privileged mode
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#define MODE_SYSTEM 0x10 // Privileged modes
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#define MODE_IRQ 0x11
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#define MODE_FIQ 0x12
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#define MODE_SUPERVISOR 0x13
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#define MODE_ABORT 0x14
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#define MODE_UNDEFINED 0x15
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#define MODE_INVALID 0x16
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// Discards privilege bit
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#define REG_MODE(m) (reg_mode[(m) & 0xF])
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#define REG_SPSR(m) (spsr[(m) & 0xF])
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#define PRIVMODE(m) ((m) >> 4)
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#define CPU_ACTIVE 0
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#define CPU_HALT 1
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#define CPU_STOP 2
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#define CPU_DMA 3 /* CPU is idling due to DMA transfer */
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typedef u8 cpu_alert_type;
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#define CPU_ALERT_NONE 0
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#define CPU_ALERT_HALT (1 << 0)
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#define CPU_ALERT_SMC (1 << 1)
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#define CPU_ALERT_IRQ (1 << 2)
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typedef u16 irq_type;
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#define IRQ_NONE 0x0000
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#define IRQ_VBLANK 0x0001
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#define IRQ_HBLANK 0x0002
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#define IRQ_VCOUNT 0x0004
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#define IRQ_TIMER0 0x0008
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#define IRQ_TIMER1 0x0010
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#define IRQ_TIMER2 0x0020
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#define IRQ_TIMER3 0x0040
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#define IRQ_SERIAL 0x0080
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#define IRQ_DMA0 0x0100
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#define IRQ_DMA1 0x0200
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#define IRQ_DMA2 0x0400
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#define IRQ_DMA3 0x0800
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#define IRQ_KEYPAD 0x1000
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#define IRQ_GAMEPAK 0x2000
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typedef enum
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{
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// CPU status & registers
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REG_SP = 13,
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REG_LR = 14,
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REG_PC = 15,
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REG_CPSR = 16,
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CPU_MODE = 17,
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CPU_HALT_STATE = 18,
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REG_ARCH_COUNT = 19,
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// This is saved separately
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REG_BUS_VALUE = 19,
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// Dynarec signaling and spilling
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// (Not really part of the CPU state)
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REG_N_FLAG = 20,
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REG_Z_FLAG = 21,
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REG_C_FLAG = 22,
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REG_V_FLAG = 23,
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REG_SLEEP_CYCLES = 24,
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OAM_UPDATED = 25,
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REG_SAVE = 26,
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REG_SAVE2 = 27,
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REG_SAVE3 = 28,
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REG_SAVE4 = 29,
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REG_SAVE5 = 30,
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REG_SAVE6 = 31,
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/* Machine defined storage */
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REG_USERDEF = 32,
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REG_MAX = 64
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} ext_reg_numbers;
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extern u32 instruction_count;
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void execute_arm(u32 cycles);
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u32 check_and_raise_interrupts(void);
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cpu_alert_type check_interrupt(void);
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cpu_alert_type flag_interrupt(irq_type irq_raised);
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void set_cpu_mode(cpu_mode_type new_mode);
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u32 function_cc execute_load_u8(u32 address);
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u32 function_cc execute_load_u16(u32 address);
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u32 function_cc execute_load_u32(u32 address);
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u32 function_cc execute_load_s8(u32 address);
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u32 function_cc execute_load_s16(u32 address);
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void function_cc execute_store_u8(u32 address, u32 source);
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void function_cc execute_store_u16(u32 address, u32 source);
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void function_cc execute_store_u32(u32 address, u32 source);
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void function_cc execute_store_aligned_u32(u32 address, u32 source);
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u32 execute_arm_translate(u32 cycles);
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void init_translater(void);
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bool cpu_check_savestate(const u8 *src);
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unsigned cpu_write_savestate(u8* dst);
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bool cpu_read_savestate(const u8 *src);
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u8 function_cc *block_lookup_address_arm(u32 pc);
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u8 function_cc *block_lookup_address_thumb(u32 pc);
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u8 function_cc *block_lookup_address_dual(u32 pc);
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bool translate_block_arm(u32 pc, bool ram_region);
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bool translate_block_thumb(u32 pc, bool ram_region);
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#if defined(MMAP_JIT_CACHE)
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extern u8* rom_translation_cache;
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extern u8* ram_translation_cache;
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#elif defined(_3DS)
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#define rom_translation_cache ((u8*)0x02000000 - ROM_TRANSLATION_CACHE_SIZE)
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#define ram_translation_cache (rom_translation_cache - RAM_TRANSLATION_CACHE_SIZE)
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extern u8* rom_translation_cache_ptr;
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extern u8* ram_translation_cache_ptr;
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#elif defined(VITA)
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extern u8* rom_translation_cache;
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extern u8* ram_translation_cache;
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extern int sceBlock;
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#else
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extern u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE];
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extern u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE];
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#endif
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extern u8 *rom_translation_ptr;
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extern u8 *ram_translation_ptr;
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#define MAX_TRANSLATION_GATES 8
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extern u32 idle_loop_target_pc;
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extern u32 translation_gate_targets;
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extern u32 translation_gate_target_pc[MAX_TRANSLATION_GATES];
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extern u32 rom_branch_hash[ROM_BRANCH_HASH_SIZE];
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void flush_translation_cache_rom(void);
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void flush_translation_cache_ram(void);
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void dump_translation_cache(void);
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void init_dynarec_caches(void);
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void flush_dynarec_caches(void);
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void init_emitter(bool);
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void init_bios_hooks(void);
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extern u32 reg_mode[7][7];
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extern u32 spsr[6];
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extern const u32 cpu_modes[16];
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extern const u32 cpsr_masks[4][2];
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extern const u32 spsr_masks[4];
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void init_cpu(void);
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void move_reg();
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extern const u8 bit_count[256];
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#endif
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