David Guillen Fandos 61ef776fed [x86] Fix CPSR store bug in LR register ... There's a race condition on CPSR store (only if mode is changed) where, if an IRQ is pending, the IRQ will be served, but the saved LR value will be wrong (will skip the return instruction). Fixed this and improved the logic a bit to make it faster and not use unnecessary save slots.		2021-12-10 19:09:20 +01:00
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x86_emit.h	[x86] Fix CPSR store bug in LR register	2021-12-10 19:09:20 +01:00
x86_stub.S	[x86] Fix CPSR store bug in LR register	2021-12-10 19:09:20 +01:00