639 lines
27 KiB
ArmAsm
639 lines
27 KiB
ArmAsm
# gameplaySP
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#
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# Copyright (C) 2006 Exophase <exophase@gmail.com>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#include "../gpsp_config.h"
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.align 4
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#define defsymbl(symbol) \
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.global symbol ; \
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.global _##symbol ; \
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symbol: \
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_##symbol:
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// Windows 32 bit ABI prefixes functions with underscore
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#if defined(_WIN32) && !defined(_WIN64)
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#define fnm(name) _##name
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#else
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#define fnm(name) name
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#endif
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// Convention calls are different, and register allocations, which makes it tricky
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// All functions in this file are called manually from the JIT arena (unless stated
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// otherwise), where we use our own convention call. However calls to C code must
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// follow the calling convention. x86 is built with regparm=2 to avoid stack usage.
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#if defined(__x86_64__) || defined(__amd64__)
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#define JUMP_CX_ZERO jrcxz
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#define ADDR_TYPE .quad
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#define ADDR_SIZE_BYTES 8
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#define STACK_REG %rsp
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#define FULLREG(rn) %r##rn
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#define SAVE_REGISTERS push %rbx; push %rsi; push %rdi; push %rbp
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#define REST_REGISTERS pop %rbp; pop %rdi; pop %rsi; pop %rbx
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#define REG_BASE %rbx
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#ifdef _WIN64
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#define CARG1_REG %ecx // Windows x64 ABI, of course different :D
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#define CARG2_REG %edx
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#define CARG2_REGPTR %rdx
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#define CALL_FUNC(name) \
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sub $32, %rsp; \
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call fnm(name); \
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add $32, %rsp
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#else
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#define CARG1_REG %edi // SystemV AMD64 ABI
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#define CARG2_REG %esi
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#define CARG2_REGPTR %rsi
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#define CALL_FUNC(name) \
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call fnm(name)
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#endif
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#define SETUP_ARGS mov %eax, CARG1_REG; mov %edx, CARG2_REG;
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#else
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#define JUMP_CX_ZERO jecxz
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#define ADDR_TYPE .long
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#define ADDR_SIZE_BYTES 4
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#define STACK_REG %esp
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#define FULLREG(rn) %e##rn
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#define SAVE_REGISTERS sub $8, %esp; push %ebx; push %esi; push %edi; push %ebp
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#define REST_REGISTERS pop %ebp; pop %edi; pop %esi; pop %ebx; add $8, %esp;
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#define REG_BASE %ebx
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#define CARG1_REG %eax
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#define CARG2_REG %edx
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#define CARG2_REGPTR %edx
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#define SETUP_ARGS
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#define CALL_FUNC(name) \
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call fnm(name)
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#endif
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.equ CPU_ALERT_HALT, (1 << 0)
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.equ CPU_ALERT_SMC, (1 << 1)
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.equ CPU_ALERT_IRQ, (1 << 2)
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.equ REG_SP, (13 * 4)
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.equ REG_LR, (14 * 4)
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.equ REG_PC, (15 * 4)
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.equ REG_CPSR, (16 * 4)
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.equ CPU_MODE, (17 * 4)
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.equ CPU_HALT_STATE, (18 * 4)
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.equ REG_BUS_VALUE, (19 * 4)
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.equ REG_N_FLAG, (20 * 4)
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.equ REG_Z_FLAG, (21 * 4)
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.equ REG_C_FLAG, (22 * 4)
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.equ REG_V_FLAG, (23 * 4)
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.equ COMPLETED_FRAME, (24 * 4)
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.equ OAM_UPDATED, (25 * 4)
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.equ REG_SAVE, (26 * 4)
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.equ load_u8_tbl, -(9 * 16 * ADDR_SIZE_BYTES)
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.equ load_s8_tbl, -(8 * 16 * ADDR_SIZE_BYTES)
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.equ load_u16_tbl, -(7 * 16 * ADDR_SIZE_BYTES)
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.equ load_s16_tbl, -(6 * 16 * ADDR_SIZE_BYTES)
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.equ load_u32_tbl, -(5 * 16 * ADDR_SIZE_BYTES)
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.equ store_u8_tbl, -(4 * 16 * ADDR_SIZE_BYTES)
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.equ store_u16_tbl, -(3 * 16 * ADDR_SIZE_BYTES)
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.equ store_u32_tbl, -(2 * 16 * ADDR_SIZE_BYTES)
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.equ store_aligned_u32_tbl, -(1 * 16 * ADDR_SIZE_BYTES)
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.equ PALETTE_RAM_OFF, 0x0100
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.equ PALETTE_RAM_CNV_OFF, 0x0500
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.equ OAM_RAM_OFF, 0x0900
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.equ IWRAM_OFF, 0x0D00
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.equ VRAM_OFF, 0x10D00
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.equ EWRAM_OFF, 0x28D00
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.equ IORAM_OFF, 0xA8D00
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.equ SPSR_OFF, 0xA9100
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.equ RDMAP_OFF, 0xA9200
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#define REG_CYCLES %ebp
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# destroys ecx and edx
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.macro collapse_flag offset, shift
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mov \offset(REG_BASE), %ecx
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shl $\shift, %ecx
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or %ecx, %edx
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.endm
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.macro collapse_flags_no_update
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xor %edx, %edx
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collapse_flag REG_N_FLAG, 31
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collapse_flag REG_Z_FLAG, 30
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collapse_flag REG_C_FLAG, 29
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collapse_flag REG_V_FLAG, 28
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mov REG_CPSR(REG_BASE), %ecx
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and $0xFF, %ecx
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or %ecx, %edx
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.endm
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.macro collapse_flags
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collapse_flags_no_update
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mov %edx, REG_CPSR(REG_BASE)
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.endm
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.macro extract_flag shift, offset
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mov REG_CPSR(REG_BASE), %edx
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shr $\shift, %edx
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and $0x01, %edx
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mov %edx, \offset(REG_BASE)
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.endm
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.macro extract_flags
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extract_flag 31, REG_N_FLAG
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extract_flag 30, REG_Z_FLAG
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extract_flag 29, REG_C_FLAG
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extract_flag 28, REG_V_FLAG
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.endm
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# Process a hardware event. Since an interrupt might be
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# raised we have to check if the PC has changed.
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# arg0 (always in eax): current PC address
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defsymbl(x86_update_gba)
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mov %eax, REG_PC(REG_BASE) # current PC = eax
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collapse_flags # update cpsr, trashes ecx and edx
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mov REG_CYCLES, CARG1_REG # Load remaining cycles as arg0
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CALL_FUNC(update_gba) # process the next event
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mov %eax, REG_CYCLES # new cycle count
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and $0x7fff, REG_CYCLES # in the lowest bits
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# did we just complete a frame? go back to main then
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cmpl $0, COMPLETED_FRAME(REG_BASE)
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jne return_to_main
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# did the PC change?
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test %eax, %eax # Bit 31 set, means need to re-fetch
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js lookup_pc
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ret # otherwise, go back to caller
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# Perform this on an indirect branch that will definitely go to
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# ARM code, IE anything that changes the PC in ARM mode except
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# for BX and data processing to PC with the S bit set.
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# arg0 (always in eax): GBA address to branch to
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defsymbl(x86_indirect_branch_arm)
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mov %eax, CARG1_REG
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CALL_FUNC(block_lookup_address_arm)
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add $ADDR_SIZE_BYTES, STACK_REG # remove current return addr
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jmp *FULLREG(ax)
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# For indirect branches that'll definitely go to Thumb. In
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# Thumb mode any indirect branches except for BX.
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# arg0 (always in eax): GBA address to branch to
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defsymbl(x86_indirect_branch_thumb)
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mov %eax, CARG1_REG
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CALL_FUNC(block_lookup_address_thumb)
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add $ADDR_SIZE_BYTES, STACK_REG # remove current return addr
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jmp *FULLREG(ax)
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# For indirect branches that can go to either Thumb or ARM,
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# mainly BX (also data processing to PC with S bit set, be
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# sure to adjust the target with a 1 in the lowest bit for this)
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# arg0 (always in eax): GBA address to branch to
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defsymbl(x86_indirect_branch_dual)
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mov %eax, CARG1_REG
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CALL_FUNC(block_lookup_address_dual)
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add $ADDR_SIZE_BYTES, STACK_REG # remove current return addr
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jmp *FULLREG(ax)
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# General ext memory routines
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ext_store_rtc8: # No RTC writes on byte or word access
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ext_store_rtc32:
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ext_store_backup16: # Backup (flash) accessed via byte writes
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ext_store_backup32:
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ext_store_ignore:
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ret # ignore these writes
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ext_store_rtc16:
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and $0xFFFF, %edx # make value 16bit
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and $0xFF, %eax # mask address
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SETUP_ARGS # Setup addr, value
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CALL_FUNC(write_rtc) # write out RTC register
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ret
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ext_store_backup8:
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and $0xFF, %edx # make value 8bit
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and $0xFFFF, %eax # mask address
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SETUP_ARGS # Setup addr, value
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CALL_FUNC(write_backup) # perform backup write
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ret
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# Handle I/O write side-effects:
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# SMC: Flush RAM caches
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# IRQ: Perform CPU mode change
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# HLT: spin in the cpu_sleep_loop until an IRQ is triggered
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write_epilogue:
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mov %eax, REG_SAVE(REG_BASE)# Save ret value for later use
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collapse_flags # Consolidate CPSR
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test $CPU_ALERT_SMC, %eax # Check for CPU_ALERT_SMC bit
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jz 1f # skip if not set
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CALL_FUNC(flush_translation_cache_ram)
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1:
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testl $CPU_ALERT_IRQ, REG_SAVE(REG_BASE) # Check for CPU_ALERT_IRQ bit
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jz 2f # skip if not set
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CALL_FUNC(check_and_raise_interrupts)
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2:
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testl $CPU_ALERT_HALT, REG_SAVE(REG_BASE) # Check for CPU_ALERT_HALT bit
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jz lookup_pc # if not halt, continue executing
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# explicit fallthrough to cpu_sleep_loop, while CPU is halted
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cpu_sleep_loop:
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mov REG_CYCLES, CARG1_REG # Load remaining cycles as arg0
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CALL_FUNC(update_gba) # process the next event
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# did we just complete a frame? go back to main then
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cmpl $0, COMPLETED_FRAME(REG_BASE)
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jne return_to_main
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// if we are out of update_gba and did not complete a frame, cpu is active
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mov %eax, REG_CYCLES # load new cycle count
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and $0x7fff, REG_CYCLES # (only lowest bits)
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jmp lookup_pc # pc changes after a halt
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ext_store_eeprom:
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CALL_FUNC(write_eeprom) # perform eeprom write
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ret
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# Register wrapping for various sizes
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#define reg32(n) %e##n##x
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#define reg16(n) %##n##x
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#define reg8(n) %##n##l
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# 16 bit bus results in duplicated 8bit accesses
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#define dup8() mov %dl, %dh
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#define noop()
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# Writes to EWRAM and IWRAM must check for SMC
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#define smc_check_store_aligned(opsuf, addrexp)
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#define smc_check_store(opsuf, addrexp) ;\
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cmp##opsuf $0, addrexp /* Check SMC mirror */ ;\
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jne smc_write
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# Memory write routines
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#define write_stubs(fname, wsize, opsuf, regfn, regfn16, addrm, dup8fn) ;\
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;\
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/* eax: address to write to */ ;\
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/* edx: value to write */ ;\
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;\
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defsymbl(execute_##fname##_u##wsize) ;\
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mov %eax, %ecx /* ecx = address */ ;\
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shr $24, %ecx /* ecx = address >> 24 */ ;\
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cmp $15, %ecx ;\
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ja ext_store_ignore ;\
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/* ecx = ext_store_u*_jtable[address >> 24] */ ;\
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jmp *fname##_u##wsize##_tbl(REG_BASE, FULLREG(cx), ADDR_SIZE_BYTES) ;\
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;\
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ext_##fname##_iwram##wsize: ;\
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and $(0x7FFF & addrm), %eax /* Addr wrap */ ;\
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mov regfn(d), (IWRAM_OFF+0x8000)(REG_BASE, FULLREG(ax)) /* Actual write */ ;\
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smc_check_##fname(opsuf, IWRAM_OFF(REG_BASE, FULLREG(ax))) ;\
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ret ;\
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;\
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ext_##fname##_ewram##wsize: ;\
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and $(0x3FFFF & addrm), %eax /* Addr wrap */ ;\
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mov regfn(d), EWRAM_OFF(REG_BASE, FULLREG(ax)) /* Actual write */ ;\
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smc_check_##fname(opsuf, (EWRAM_OFF+0x40000)(REG_BASE, FULLREG(ax))) ;\
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ret ;\
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;\
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ext_##fname##_vram##wsize: ;\
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and $(0x1FFFE & addrm), %eax /* Addr wrap */ ;\
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dup8fn() /* Double byte for 8b access */ ;\
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cmp $0x18000, %eax /* Weird 96KB mirror */ ;\
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jb 1f ;\
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sub $0x8000, %eax /* Mirror last bank */ ;\
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1: ;\
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mov regfn16(d), VRAM_OFF(REG_BASE, FULLREG(ax)) /* Actual write */ ;\
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ret ;\
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;\
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ext_##fname##_oam##wsize: ;\
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and $(0x3FE & addrm), %eax /* Addr wrap */ ;\
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movl $1, OAM_UPDATED(REG_BASE) /* flag OAM update */ ;\
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dup8fn() /* Double byte for 8b access */ ;\
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mov regfn16(d), OAM_RAM_OFF(REG_BASE, FULLREG(ax)) /* Actual write */ ;\
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ret ;\
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;\
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ext_##fname##_io##wsize: ;\
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and $(0x3FF & addrm), %eax /* Addr wrap */ ;\
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SETUP_ARGS ;\
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CALL_FUNC(write_io_register##wsize) /* Call C code */ ;\
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cmp $0, %eax /* Check for side-effects */ ;\
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jnz write_epilogue /* Act on SMC and IRQs */ ;\
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ret ;\
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write_stubs(store, 32, l, reg32, reg32, ~3, noop)
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write_stubs(store, 16, w, reg16, reg16, ~1, noop)
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write_stubs(store, 8, b, reg8, reg16, ~0, dup8)
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write_stubs(store_aligned, 32, l, reg32, reg32, ~3, noop)
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# Palette routines are a bit special, due to 16bit bus + decoded palette
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ext_store_palette8:
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and $0x3FE, %eax # wrap around address and align to 16bits
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mov %dl, %dh # duplicate the byte to be written
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jmp ext_store_palette16b # perform 16bit palette write
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ext_store_palette16:
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and $0x3FF, %eax # wrap around address
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ext_store_palette16b: # entry point for 8bit write
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mov %dx, PALETTE_RAM_OFF(REG_BASE, FULLREG(ax)) # write out palette value
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mov %edx, %ecx # cx = dx
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shl $11, %ecx # cx <<= 11 (red component is in high bits)
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mov %dh, %cl # bottom bits of cx = top bits of dx
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shr $2, %cl # move the blue component to the bottom of cl
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and $0x03E0, %dx # isolate green component of dx
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shl $1, %dx # make green component 6bits
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or %edx, %ecx # combine green component into ecx
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# write out the freshly converted palette value
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mov %cx, PALETTE_RAM_CNV_OFF(REG_BASE, FULLREG(ax))
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ret # done
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ext_store_palette32:
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and $0x3FF, %eax # wrap around address
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call ext_store_palette16b # write first 16bits
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add $2, %eax # go to next address
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shr $16, %edx # go to next 16bits
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jmp ext_store_palette16b # write next 16bits
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# Memory load routines
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#define load_stubs(rtype, movop, addrm, albits, slowfn) ;\
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;\
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/* eax: address to read */ ;\
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/* edx: current PC address */ ;\
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;\
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defsymbl(execute_load_##rtype) ;\
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mov %eax, %ecx /* ecx = address */ ;\
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rol $8, %ecx /* ecx = ror(address, 24) */ ;\
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and $((1<<(8+albits))-1), %ecx /* preserve align+msb */ ;\
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cmp $15, %ecx ;\
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ja ext_load_slow##rtype ;\
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jmp *load_##rtype##_tbl(REG_BASE, FULLREG(cx), ADDR_SIZE_BYTES) ;\
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;\
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ext_load_iwram##rtype: ;\
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and $(0x7FFF & addrm), %eax /* Addr wrap */ ;\
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movop (IWRAM_OFF+0x8000)(REG_BASE, FULLREG(ax)), %eax /* Read mem */ ;\
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ret ;\
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;\
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ext_load_ewram##rtype: ;\
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and $(0x3FFFF & addrm), %eax /* Addr wrap */ ;\
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movop EWRAM_OFF(REG_BASE, FULLREG(ax)), %eax /* Read mem */ ;\
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ret ;\
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;\
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ext_load_vram##rtype: ;\
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and $(0x1FFFF & addrm), %eax /* Addr wrap */ ;\
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cmp $0x18000, %eax /* Weird 96KB mirror */ ;\
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jb 1f ;\
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sub $0x8000, %eax /* Mirror last bank */ ;\
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1: ;\
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movop VRAM_OFF(REG_BASE, FULLREG(ax)), %eax /* Read mem */ ;\
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ret ;\
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;\
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ext_load_oam##rtype: ;\
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and $(0x3FF & addrm), %eax /* Addr wrap */ ;\
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movop OAM_RAM_OFF(REG_BASE, FULLREG(ax)), %eax /* Read mem */ ;\
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ret ;\
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;\
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ext_load_palette##rtype: ;\
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and $(0x3FF & addrm), %eax /* Addr wrap */ ;\
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movop PALETTE_RAM_OFF(REG_BASE, FULLREG(ax)), %eax /* Read mem */ ;\
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ret ;\
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;\
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ext_load_io##rtype: ;\
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and $(0x3FF & addrm), %eax /* Addr wrap */ ;\
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movop IORAM_OFF(REG_BASE, FULLREG(ax)), %eax /* Read mem */ ;\
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ret ;\
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;\
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ext_load_rom##rtype: ;\
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mov %eax, %esi /* esi = address */ ;\
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shr $15, %esi /* esi = address >> 15 */ ;\
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/* Read rdmap pointer */ ;\
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mov RDMAP_OFF(REG_BASE, FULLREG(si), ADDR_SIZE_BYTES), FULLREG(cx) ;\
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JUMP_CX_ZERO ext_load_slow##rtype /* page not loaded, slow */ ;\
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mov %eax, %edx /* edx = address */ ;\
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and $0x7FFF, %edx /* edx = address LSB */ ;\
|
|
movop (FULLREG(cx), FULLREG(dx)), %eax /* Read mem */ ;\
|
|
ret ;\
|
|
;\
|
|
ext_load_slow##rtype: ;\
|
|
mov %edx, REG_PC(REG_BASE) /* Store current PC */ ;\
|
|
SETUP_ARGS ;\
|
|
CALL_FUNC(slowfn) ;\
|
|
ret ;\
|
|
|
|
load_stubs(u32, mov, ~3, 2, read_memory32)
|
|
load_stubs(u16, movzwl, ~1, 1, read_memory16)
|
|
load_stubs(s16, movswl, ~1, 1, read_memory16s)
|
|
load_stubs( u8, movzbl, ~0, 0, read_memory8)
|
|
load_stubs( s8, movsbl, ~0, 0, read_memory8s)
|
|
|
|
|
|
# arg0 (%eax) = new_cpsr
|
|
# arg1 (%edx) = store_mask (user mode)
|
|
# arg2 (%ecx) = store_mask (system mode)
|
|
defsymbl(execute_store_cpsr)
|
|
testl $0x10, CPU_MODE(REG_BASE) # check privileged mode bit
|
|
cmovne %ecx, %edx # use system mode mask if set
|
|
|
|
mov %edx, %esi # save store_mask for later
|
|
|
|
mov %eax, %ecx # ecx = new_cpsr
|
|
and %edx, %ecx # ecx = new_cpsr & store_mask
|
|
mov REG_CPSR(REG_BASE), %eax # eax = cpsr
|
|
not %edx # edx = ~store_mask
|
|
and %edx, %eax # eax = cpsr & ~store_mask
|
|
or %ecx, %eax # eax = new cpsr combined with old
|
|
mov %eax, REG_CPSR(REG_BASE) # save new cpsr to register
|
|
|
|
# Check whether any side effects (IRQ) could have happened
|
|
test $0xff, %esi
|
|
jnz 1f
|
|
extract_flags # pull out flag vars from new CPSR
|
|
ret
|
|
1:
|
|
CALL_FUNC(execute_store_cpsr_body) # do the dirty work in this C function
|
|
extract_flags # pull out flag vars from new CPSR
|
|
cmp $0, %eax # see if return value is 0
|
|
jnz 2f # might have changed the PC
|
|
ret # return
|
|
2: # PC has changed, due to IRQ triggered
|
|
mov %eax, CARG1_REG # Returned addr from C function
|
|
CALL_FUNC(block_lookup_address_arm) # lookup new PC
|
|
add $ADDR_SIZE_BYTES, STACK_REG # get rid of current return address
|
|
jmp *FULLREG(ax)
|
|
|
|
|
|
# On writes that overwrite code, cache is flushed and execution re-started
|
|
smc_write:
|
|
CALL_FUNC(flush_translation_cache_ram)
|
|
lookup_pc:
|
|
mov REG_PC(REG_BASE), CARG1_REG # Load PC as argument0
|
|
testl $0x20, REG_CPSR(REG_BASE)
|
|
jz 1f
|
|
### Thumb mode
|
|
CALL_FUNC(block_lookup_address_thumb)
|
|
add $ADDR_SIZE_BYTES, STACK_REG # Can't return, discard addr
|
|
jmp *FULLREG(ax)
|
|
1:# ARM mode
|
|
CALL_FUNC(block_lookup_address_arm)
|
|
add $ADDR_SIZE_BYTES, STACK_REG # Can't return, discard addr
|
|
jmp *FULLREG(ax)
|
|
|
|
# Called from C, args are platform dependant :/
|
|
# arg0 (eax/edi/ecx): cycle counter
|
|
# arg1 (edx/rsi/rdx): reg base pointer
|
|
|
|
defsymbl(execute_arm_translate_internal)
|
|
# Save main context, since we need to return gracefully
|
|
SAVE_REGISTERS # Pushes 16 or 32 bytes
|
|
# The stack here is aligned to 16 bytes minus 4 or 8 bytes.
|
|
|
|
mov CARG1_REG, REG_CYCLES # load cycle counter (arg0)
|
|
mov CARG2_REGPTR, REG_BASE # load base register (arg1)
|
|
|
|
extract_flags # load flag variables
|
|
|
|
# (if the CPU is halted, do not start executing but
|
|
# loop in the alert loop until it wakes up)
|
|
cmpl $0, CPU_HALT_STATE(REG_BASE)
|
|
je 1f
|
|
call cpu_sleep_loop # Need to push something to the stack
|
|
|
|
1:
|
|
call lookup_pc # Go fetch and execute PC
|
|
|
|
return_to_main:
|
|
add $ADDR_SIZE_BYTES, STACK_REG # remove current return addr
|
|
REST_REGISTERS # Restore saved registers
|
|
ret
|
|
|
|
#define load_table(atype) ;\
|
|
ADDR_TYPE ext_load_slow##atype /* 0x00 BIOS */;\
|
|
ADDR_TYPE ext_load_slow##atype /* 0x01 open read */;\
|
|
ADDR_TYPE ext_load_ewram##atype /* 0x02 EWRAM */;\
|
|
ADDR_TYPE ext_load_iwram##atype /* 0x03 IWRAM */;\
|
|
ADDR_TYPE ext_load_io##atype /* 0x04 I/O registers */;\
|
|
ADDR_TYPE ext_load_palette##atype /* 0x05 Palette RAM */;\
|
|
ADDR_TYPE ext_load_vram##atype /* 0x06 VRAM */;\
|
|
ADDR_TYPE ext_load_oam##atype /* 0x07 OAM RAM */;\
|
|
ADDR_TYPE ext_load_rom##atype /* 0x08 gamepak (or RTC) */;\
|
|
ADDR_TYPE ext_load_rom##atype /* 0x09 gamepak */;\
|
|
ADDR_TYPE ext_load_rom##atype /* 0x0A gamepak */;\
|
|
ADDR_TYPE ext_load_rom##atype /* 0x0B gamepak */;\
|
|
ADDR_TYPE ext_load_rom##atype /* 0x0C gamepak */;\
|
|
ADDR_TYPE ext_load_slow##atype /* 0x0D EEPROM (possibly) */;\
|
|
ADDR_TYPE ext_load_slow##atype /* 0x0E Flash ROM/SRAM */;\
|
|
ADDR_TYPE ext_load_slow##atype /* 0x0F open read */;\
|
|
|
|
#define store_table(asize) ;\
|
|
ADDR_TYPE ext_store_ignore /* 0x00 BIOS, ignore */;\
|
|
ADDR_TYPE ext_store_ignore /* 0x01 invalid, ignore */;\
|
|
ADDR_TYPE ext_store_ewram##asize /* 0x02 EWRAM */;\
|
|
ADDR_TYPE ext_store_iwram##asize /* 0x03 IWRAM */;\
|
|
ADDR_TYPE ext_store_io##asize /* 0x04 I/O registers */;\
|
|
ADDR_TYPE ext_store_palette##asize /* 0x05 Palette RAM */;\
|
|
ADDR_TYPE ext_store_vram##asize /* 0x06 VRAM */;\
|
|
ADDR_TYPE ext_store_oam##asize /* 0x07 OAM RAM */;\
|
|
ADDR_TYPE ext_store_rtc##asize /* 0x08 gamepak (RTC or ignore) */;\
|
|
ADDR_TYPE ext_store_ignore /* 0x09 gamepak, ignore */;\
|
|
ADDR_TYPE ext_store_ignore /* 0x0A gamepak, ignore */;\
|
|
ADDR_TYPE ext_store_ignore /* 0x0B gamepak, ignore */;\
|
|
ADDR_TYPE ext_store_ignore /* 0x0C gamepak, ignore */;\
|
|
ADDR_TYPE ext_store_eeprom /* 0x0D EEPROM (possibly) */;\
|
|
ADDR_TYPE ext_store_backup##asize /* 0x0E Flash ROM/SRAM */;\
|
|
ADDR_TYPE ext_store_ignore /* 0x0F ignore */;\
|
|
|
|
.data
|
|
.align 16
|
|
|
|
defsymbl(x86_table_data)
|
|
load_table(u8)
|
|
load_table(s8)
|
|
load_table(u16)
|
|
load_table(s16)
|
|
load_table(u32)
|
|
store_table(8)
|
|
store_table(16)
|
|
store_table(32)
|
|
|
|
# aligned word writes (non SMC signaling)
|
|
ADDR_TYPE ext_store_ignore # 0x00 BIOS, ignore
|
|
ADDR_TYPE ext_store_ignore # 0x01 invalid, ignore
|
|
ADDR_TYPE ext_store_aligned_ewram32 # 0x02 EWRAM
|
|
ADDR_TYPE ext_store_aligned_iwram32 # 0x03 IWRAM
|
|
ADDR_TYPE ext_store_io32 # 0x04 I/O registers
|
|
ADDR_TYPE ext_store_palette32 # 0x05 Palette RAM
|
|
ADDR_TYPE ext_store_vram32 # 0x06 VRAM
|
|
ADDR_TYPE ext_store_oam32 # 0x07 OAM RAM
|
|
ADDR_TYPE ext_store_ignore # 0x08 gamepak, ignore (no RTC in 32bit)
|
|
ADDR_TYPE ext_store_ignore # 0x09 gamepak, ignore
|
|
ADDR_TYPE ext_store_ignore # 0x0A gamepak, ignore
|
|
ADDR_TYPE ext_store_ignore # 0x0B gamepak, ignore
|
|
ADDR_TYPE ext_store_ignore # 0x0C gamepak, ignore
|
|
ADDR_TYPE ext_store_eeprom # 0x0D EEPROM (possibly)
|
|
ADDR_TYPE ext_store_ignore # 0x0E Flash ROM/SRAM must be 8bit
|
|
ADDR_TYPE ext_store_ignore # 0x0F ignore
|
|
|
|
|
|
.bss
|
|
.align 64
|
|
|
|
defsymbl(x86_table_info)
|
|
.space 9*16*ADDR_SIZE_BYTES
|
|
defsymbl(reg)
|
|
.space 0x100
|
|
defsymbl(palette_ram)
|
|
.space 0x400
|
|
defsymbl(palette_ram_converted)
|
|
.space 0x400
|
|
defsymbl(oam_ram)
|
|
.space 0x400
|
|
defsymbl(iwram)
|
|
.space 0x10000
|
|
defsymbl(vram)
|
|
.space 0x18000
|
|
defsymbl(ewram)
|
|
.space 0x80000
|
|
defsymbl(io_registers)
|
|
.space 0x400
|
|
defsymbl(spsr)
|
|
.space 24
|
|
.space 8 # padding
|
|
defsymbl(reg_mode)
|
|
.space 196
|
|
.space 28 # padding
|
|
defsymbl(memory_map_read)
|
|
.space 8*1024*ADDR_SIZE_BYTES
|
|
|
|
#ifndef MMAP_JIT_CACHE
|
|
#error "x86 dynarec builds *require* MMAP_JIT_CACHE"
|
|
#endif
|
|
|