David Guillen Fandos 33f1e25099 Emit BIOS SWI entrypoint to ROM arena ... This fixes a race condition that happens whenever the ROM cache is flushed but the RAM one is not, causing any SWI calls (implemented as direct branches) to jump to random instructions. The fix could be to flush both caches at the same time (~expensive on low mem platforms), use indirect jumps (a bit expensive) or emit the SWI handler below the watermark to ensure it is never flushed. This is cheap and effective, requires minimal changes.		2021-09-10 00:30:55 +02:00
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mips_emit.h	Emit BIOS SWI entrypoint to ROM arena	2021-09-10 00:30:55 +02:00
mips_stub.S	Merge stub arena into ROM cache for simplicity.	2021-09-09 19:06:15 +02:00