400 lines
12 KiB
C
400 lines
12 KiB
C
/* gameplaySP
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*
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* Copyright (C) 2006 Exophase <exophase@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "common.h"
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#include <ctype.h>
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timer_type timer[4];
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u32 cpu_ticks = 0;
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u32 execute_cycles = 0;
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s32 video_count = 0;
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u32 last_frame = 0;
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u32 flush_ram_count = 0;
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u32 gbc_update_count = 0;
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u32 oam_update_count = 0;
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char main_path[512];
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void trigger_ext_event(void);
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static unsigned update_timers(irq_type *irq_raised, unsigned completed_cycles)
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{
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unsigned i, ret = 0;
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for (i = 0; i < 4; i++)
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{
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if(timer[i].status == TIMER_INACTIVE)
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continue;
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if(timer[i].status != TIMER_CASCADE)
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{
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timer[i].count -= completed_cycles;
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/* io_registers accessors range: REG_TM0D, REG_TM1D, REG_TM2D, REG_TM3D */
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write_ioreg(REG_TMXD(i), -(timer[i].count >> timer[i].prescale));
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}
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if(timer[i].count > 0)
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continue;
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/* irq_raised value range: IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3 */
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if(timer[i].irq)
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*irq_raised |= (IRQ_TIMER0 << i);
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if((i != 3) && (timer[i + 1].status == TIMER_CASCADE))
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{
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timer[i + 1].count--;
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write_ioreg(REG_TMXD(i + 1), -timer[i+1].count);
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}
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if(i < 2)
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{
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if(timer[i].direct_sound_channels & 0x01)
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ret += sound_timer(timer[i].frequency_step, 0);
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if(timer[i].direct_sound_channels & 0x02)
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ret += sound_timer(timer[i].frequency_step, 1);
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}
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timer[i].count += (timer[i].reload << timer[i].prescale);
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}
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return ret;
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}
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void init_main(void)
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{
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u32 i;
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for(i = 0; i < 4; i++)
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{
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timer[i].status = TIMER_INACTIVE;
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timer[i].prescale = 0;
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timer[i].irq = 0;
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timer[i].reload = timer[i].count = 0x10000;
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timer[i].direct_sound_channels = TIMER_DS_CHANNEL_NONE;
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timer[i].frequency_step = 0;
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}
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timer[0].direct_sound_channels = TIMER_DS_CHANNEL_BOTH;
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timer[1].direct_sound_channels = TIMER_DS_CHANNEL_NONE;
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cpu_ticks = 0;
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execute_cycles = 960;
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video_count = 960;
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#ifdef HAVE_DYNAREC
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init_dynarec_caches();
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init_emitter(gamepak_must_swap());
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#endif
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}
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u32 function_cc update_gba(int remaining_cycles)
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{
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u32 changed_pc = 0;
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u32 frame_complete = 0;
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irq_type irq_raised = IRQ_NONE;
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int dma_cycles;
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trace_update_gba(remaining_cycles);
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remaining_cycles = MAX(remaining_cycles, -64);
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do
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{
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unsigned i;
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// Number of cycles we ask to run - cycles that we did not execute
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// (remaining_cycles can be negative and should be close to zero)
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unsigned completed_cycles = execute_cycles - remaining_cycles;
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cpu_ticks += completed_cycles;
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remaining_cycles = 0;
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// Timers can trigger DMA (usually sound) and consume cycles
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dma_cycles = update_timers(&irq_raised, completed_cycles);
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// Video count tracks the video cycles remaining until the next event
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video_count -= completed_cycles;
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// Ran out of cycles, move to the next video area
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if(video_count <= 0)
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{
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u32 vcount = read_ioreg(REG_VCOUNT);
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u32 dispstat = read_ioreg(REG_DISPSTAT);
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// Check if we are in hrefresh (0) or hblank (1)
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if ((dispstat & 0x02) == 0)
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{
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// Transition from hrefresh to hblank
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dispstat |= 0x02;
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video_count += (272); // hblank duration, 272 cycles
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// Check if we are drawing (0) or we are in vblank (1)
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if ((dispstat & 0x01) == 0)
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{
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u32 i;
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// Render the scan line
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if(reg[OAM_UPDATED])
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oam_update_count++;
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update_scanline();
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// Trigger the HBlank DMAs if enabled
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for (i = 0; i < 4; i++)
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{
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if(dma[i].start_type == DMA_START_HBLANK)
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dma_transfer(i, &dma_cycles);
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}
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}
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// Trigger the hblank interrupt, if enabled in DISPSTAT
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if (dispstat & 0x10)
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irq_raised |= IRQ_HBLANK;
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}
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else
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{
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// Transition from hblank to the next scan line (vdraw or vblank)
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video_count += 960;
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dispstat &= ~0x02;
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vcount++;
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if(vcount == 160)
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{
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// Transition from vrefresh to vblank
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u32 i;
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dispstat |= 0x01;
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// Reinit affine transformation counters for the next frame
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video_reload_counters();
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// Trigger VBlank interrupt if enabled
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if (dispstat & 0x8)
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irq_raised |= IRQ_VBLANK;
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// Trigger the VBlank DMAs if enabled
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for (i = 0; i < 4; i++)
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{
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if(dma[i].start_type == DMA_START_VBLANK)
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dma_transfer(i, &dma_cycles);
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}
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}
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else if (vcount == 228)
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{
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// Transition from vblank to next screen
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vcount = 0;
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dispstat &= ~0x01;
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/* If there's no cheat hook, run on vblank! */
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if (cheat_master_hook == ~0U)
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process_cheats();
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/* printf("frame update (%x), %d instructions total, %d RAM flushes\n",
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reg[REG_PC], instruction_count - last_frame, flush_ram_count);
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last_frame = instruction_count;
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*/
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/* printf("%d gbc audio updates\n", gbc_update_count);
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printf("%d oam updates\n", oam_update_count); */
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gbc_update_count = 0;
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oam_update_count = 0;
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flush_ram_count = 0;
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// Force audio generation. Need to flush samples for this frame.
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render_gbc_sound();
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// We completed a frame, tell the dynarec to exit to the main thread
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frame_complete = 0x80000000;
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}
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// Vcount trigger (flag) and IRQ if enabled
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if(vcount == (dispstat >> 8))
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{
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dispstat |= 0x04;
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if(dispstat & 0x20)
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irq_raised |= IRQ_VCOUNT;
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}
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else
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dispstat &= ~0x04;
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write_ioreg(REG_VCOUNT, vcount);
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}
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write_ioreg(REG_DISPSTAT, dispstat);
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}
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// Flag any V/H blank interrupts, DMA IRQs, Vcount, etc.
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if (irq_raised)
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flag_interrupt(irq_raised);
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// Raise any pending interrupts. This changes the CPU mode.
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if (check_and_raise_interrupts())
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changed_pc = 0x40000000;
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// Figure out when we need to stop CPU execution. The next event is
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// a video event or a timer event, whatever happens first.
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execute_cycles = MAX(video_count, 0);
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// If we are paused due to a DMA, cap the number of cyles to that amount.
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if (reg[CPU_HALT_STATE] == CPU_DMA) {
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u32 dma_cyc = reg[REG_SLEEP_CYCLES];
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// The first iteration is marked by bit 31 set, just do nothing now.
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if (dma_cyc & 0x80000000)
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dma_cyc &= 0x7FFFFFFF; // Start counting DMA cycles from now on.
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else
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dma_cyc -= MIN(dma_cyc, completed_cycles); // Account DMA cycles.
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reg[REG_SLEEP_CYCLES] = dma_cyc;
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if (!dma_cyc)
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reg[CPU_HALT_STATE] = CPU_ACTIVE; // DMA finished, resume execution.
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else
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execute_cycles = MIN(execute_cycles, dma_cyc); // Continue sleeping.
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}
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for (i = 0; i < 4; i++)
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{
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if (timer[i].status == TIMER_PRESCALE &&
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timer[i].count < execute_cycles)
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execute_cycles = timer[i].count;
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}
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} while(reg[CPU_HALT_STATE] != CPU_ACTIVE && !frame_complete);
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// We voluntarily limit this. It is not accurate but it would be much harder.
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dma_cycles = MIN(64, dma_cycles);
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dma_cycles = MIN(execute_cycles, dma_cycles);
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return (execute_cycles - dma_cycles) | changed_pc | frame_complete;
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}
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void reset_gba(void)
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{
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init_memory();
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init_main();
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init_cpu();
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reset_sound();
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}
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#ifdef TRACE_REGISTERS
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void print_regs(void)
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{
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printf("R0=%08x R1=%08x R2=%08x R3=%08x "
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"R4=%08x R5=%08x R6=%08x R7=%08x "
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"R8=%08x R9=%08x R10=%08x R11=%08x "
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"R12=%08x R13=%08x R14=%08x\n",
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reg[0], reg[1], reg[2], reg[3],
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reg[4], reg[5], reg[6], reg[7],
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reg[8], reg[9], reg[10], reg[11],
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reg[12], reg[13], reg[14]);
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}
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#endif
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bool main_check_savestate(const u8 *src)
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{
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int i;
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const u8 *p1 = bson_find_key(src, "emu");
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const u8 *p2 = bson_find_key(src, "timers");
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if (!p1 || !p2)
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return false;
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if (!bson_contains_key(p1, "cpu-ticks", BSON_TYPE_INT32) ||
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!bson_contains_key(p1, "exec-cycles", BSON_TYPE_INT32) ||
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!bson_contains_key(p1, "video-count", BSON_TYPE_INT32) ||
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!bson_contains_key(p1, "sleep-cycles", BSON_TYPE_INT32))
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return false;
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for (i = 0; i < 4; i++)
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{
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char tname[2] = {'0' + i, 0};
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const u8 *p = bson_find_key(p2, tname);
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if (!p)
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return false;
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if (!bson_contains_key(p, "count", BSON_TYPE_INT32) ||
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!bson_contains_key(p, "reload", BSON_TYPE_INT32) ||
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!bson_contains_key(p, "prescale", BSON_TYPE_INT32) ||
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!bson_contains_key(p, "freq-step", BSON_TYPE_INT32) ||
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!bson_contains_key(p, "dsc", BSON_TYPE_INT32) ||
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!bson_contains_key(p, "irq", BSON_TYPE_INT32) ||
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!bson_contains_key(p, "status", BSON_TYPE_INT32))
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return false;
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}
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return true;
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}
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bool main_read_savestate(const u8 *src)
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{
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int i;
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const u8 *p1 = bson_find_key(src, "emu");
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const u8 *p2 = bson_find_key(src, "timers");
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if (!p1 || !p2)
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return false;
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if (!(bson_read_int32(p1, "cpu-ticks", &cpu_ticks) &&
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bson_read_int32(p1, "exec-cycles", &execute_cycles) &&
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bson_read_int32(p1, "video-count", (u32*)&video_count) &&
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bson_read_int32(p1, "sleep-cycles", ®[REG_SLEEP_CYCLES])))
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return false;
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for (i = 0; i < 4; i++)
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{
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char tname[2] = {'0' + i, 0};
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const u8 *p = bson_find_key(p2, tname);
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if (!(
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bson_read_int32(p, "count", (u32*)&timer[i].count) &&
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bson_read_int32(p, "reload", &timer[i].reload) &&
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bson_read_int32(p, "prescale", &timer[i].prescale) &&
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bson_read_int32(p, "freq-step", &timer[i].frequency_step) &&
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bson_read_int32(p, "dsc", &timer[i].direct_sound_channels) &&
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bson_read_int32(p, "irq", &timer[i].irq) &&
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bson_read_int32(p, "status", &timer[i].status)))
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return false;
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}
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return true;
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}
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unsigned main_write_savestate(u8* dst)
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{
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int i;
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u8 *wbptr, *wbptr2, *startp = dst;
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bson_start_document(dst, "emu", wbptr);
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bson_write_int32(dst, "cpu-ticks", cpu_ticks);
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bson_write_int32(dst, "exec-cycles", execute_cycles);
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bson_write_int32(dst, "video-count", video_count);
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bson_write_int32(dst, "sleep-cycles", reg[REG_SLEEP_CYCLES]);
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bson_finish_document(dst, wbptr);
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bson_start_document(dst, "timers", wbptr);
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for (i = 0; i < 4; i++)
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{
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char tname[2] = {'0' + i, 0};
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bson_start_document(dst, tname, wbptr2);
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bson_write_int32(dst, "count", timer[i].count);
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bson_write_int32(dst, "reload", timer[i].reload);
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bson_write_int32(dst, "prescale", timer[i].prescale);
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bson_write_int32(dst, "freq-step", timer[i].frequency_step);
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bson_write_int32(dst, "dsc", timer[i].direct_sound_channels);
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bson_write_int32(dst, "irq", timer[i].irq);
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bson_write_int32(dst, "status", timer[i].status);
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bson_finish_document(dst, wbptr2);
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}
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bson_finish_document(dst, wbptr);
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return (unsigned int)(dst - startp);
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}
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