bcd3d1ca29
This is based on the MIPS dynarec (more or less) with some ARM borrowings. Seems to be quite fast (under my testing fixed results: faster than ARM on A1 but not a lot faster than the interpreter on Android Snapdragon 845) but still some optimizations are missing at the moment. Seems to pass my testing suite and compatibility wise is very similar to arm.
208 lines
3 KiB
ArmAsm
208 lines
3 KiB
ArmAsm
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b 16*4
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bl 16*4
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b.eq 16*4
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b.ne 16*4
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b.hs 16*4
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b.lo 16*4
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b.mi 16*4
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b.pl 16*4
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b.vs 16*4
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b.vc 16*4
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b.hi 16*4
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b.ls 16*4
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b.ge 16*4
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b.lt 16*4
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b.gt 16*4
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b.le 16*4
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b.al 16*4
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b.nv 16*4
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ldr w1, [x2, #64]
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ldr w29, [x30, #64]
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str w1, [x2, #64]
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str w29, [x30, #64]
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mov w0, #0x1234
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mov w12, #0x5656
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mov w12, #0xFFFF
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movk w13, #0x9876, lsl #16
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movk w13, #0xFFFF, lsl #16
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movz w13, #0xabcd, lsl #16
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mov w14, #0xffff5555
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add w11, w12, w13, lsl #0
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add w11, w12, w13, lsl #19
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add w11, w12, w13, lsl #31
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add w1, w29, #0x123
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add w1, w29, #0xFFF
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sub w1, w29, #0x123
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sub w1, w29, #0xFFF
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add w3, w30, #0x123000
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add w3, w30, #0xFFF000
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sub w3, w30, #0x123000
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sub w3, w30, #0xFFF000
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adds w29, w30, #0x123
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adds w29, w30, #0xFFF
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subs w29, w30, #0x123
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subs w29, w30, #0xFFF
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madd w2, w3, w4, w5
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madd w25, w26, w27, w28
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msub w2, w3, w4, w5
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msub w25, w26, w27, w28
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smaddl x2, w3, w4, x5
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smaddl x25, w26, w27, x28
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umaddl x2, w3, w4, x5
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umaddl x25, w26, w27, x28
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mul w1, w2, w3
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mul w27, w28, w29
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ror w1, w2, #1
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ror w1, w2, #31
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ror w30, w29, #1
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ror w30, w29, #31
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lsr w1, w2, #1
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lsr w1, w2, #31
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lsr w30, w29, #1
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lsr w30, w29, #31
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lsl w1, w2, #1
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lsl w1, w2, #31
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lsl w30, w29, #1
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lsl w30, w29, #31
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asr w1, w2, #1
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asr w1, w2, #31
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asr w30, w29, #1
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asr w30, w29, #31
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lsr x1, x2, #1
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lsr x1, x2, #2
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lsr x1, x2, #62
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lsr x1, x2, #63
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lsr x30, x29, #1
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lsr x30, x29, #62
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eor w3, w4, #1
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eor w3, w4, #(~1)
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orr w3, w4, #1
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orr w3, w4, #(~1)
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and w3, w4, #1
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and w3, w4, #(~3)
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and x3, x4, #0xffffffff
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and x3, x4, #0x1
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and x1, x2, #1
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and x1, x2, #(~1)
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and x1, x2, #0xffffffff
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mov w1, w2
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mov w30, wzr
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orr w1, w2, w3
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orr w29, w30, wzr
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eor w1, w2, w3
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eor w29, w30, wzr
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orn w1, w2, w3
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orn w29, w30, wzr
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and w1, w2, w3
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and w29, w30, wzr
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bic w1, w2, w3
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bic w29, w30, wzr
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ands w1, w2, w3
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ands w29, w30, wzr
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tst w1, w2
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tst w25, wzr
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cmp w1, #0
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cmp w30, #0
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cmp w1, #32
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cmp w30, #32
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cmp w1, #200
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cmp w30, #200
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add w1, w2, w3
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add w29, w30, w28
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sub w1, w2, w3
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sub w29, w30, w28
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adc w1, w2, w3
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adc w29, w30, w28
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sbc w1, w2, w3
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sbc w29, w30, w28
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adds w1, w2, w3
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adds w29, w30, w28
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subs w1, w2, w3
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subs w29, w30, w28
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adcs w1, w2, w3
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adcs w29, w30, w28
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sbcs w1, w2, w3
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sbcs w29, w30, w28
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tbz w20, #1, 63*4
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tbnz w20, #1, 63*4
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tbz w20, #0, 2*4
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tbnz w20, #7, 2*4
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cbz w20, 63*4
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cbnz w20, 63*4
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cbz w20, 2*4
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cbnz w20, 2*4
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csel w20, w24, w25, ne
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csel w1, w2, w3, eq
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csel w1, w20, wzr, lt
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csel w1, wzr, wzr, gt
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csinc w20, w24, w25, ne
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csinc w1, w2, w3, eq
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csinc w1, w20, wzr, lt
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csinc w1, wzr, wzr, gt
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csinv w20, w24, w25, ne
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csinv w1, w2, w3, eq
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csinv w1, w20, wzr, lt
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csinv w1, wzr, wzr, gt
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csneg w20, w24, w25, ne
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csneg w1, w2, w3, eq
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csneg w1, w20, wzr, lt
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csneg w1, wzr, wzr, gt
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cset w1, eq
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cset w1, hs
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cset w20, lo
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csetm w1, hs
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csetm w20, lo
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ubfx w1, w2, #8, #8
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ubfx w1, w2, #16, #16
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ubfx w1, wzr, #8, #24
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ubfx w1, wzr, #16, #16
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rorv w1, w2, w3
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rorv w28, w29, w30
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lslv w1, w2, w3
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lslv w28, w29, w30
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lsrv w1, w2, w3
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lsrv w28, w29, w30
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asrv w1, w2, w3
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asrv w28, w29, w30
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orr x1, x2, x3, lsl #32
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orr x25, x26, x27, lsl #32
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sdiv w1, w2, w3
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sdiv w28, w29, w30
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