971 lines
40 KiB
ArmAsm
971 lines
40 KiB
ArmAsm
.align 2
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.global arm_update_gba_arm
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.global arm_update_gba_thumb
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.global arm_update_gba_idle_arm
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.global arm_update_gba_idle_thumb
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.global arm_indirect_branch_arm
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.global arm_indirect_branch_thumb
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.global arm_indirect_branch_dual_arm
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.global arm_indirect_branch_dual_thumb
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.global execute_arm_translate
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.global execute_store_u8
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.global execute_store_u16
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.global execute_store_u32
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.global execute_store_u32_safe
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.global execute_load_u8
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.global execute_load_s8
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.global execute_load_u16
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.global execute_load_s16
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.global execute_load_u32
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.global execute_store_cpsr
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.global execute_read_spsr
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.global execute_store_spsr
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.global execute_spsr_restore
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.global execute_swi_arm
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.global execute_swi_thumb
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.global execute_patch_bios_read
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.global execute_patch_bios_protect
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.global execute_bios_ptr_protected
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.global execute_bios_rom_ptr
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.global step_debug_arm
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.global invalidate_icache_region
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.global invalidate_cache_region
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.global memory_map_read
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.global memory_map_write
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.global reg
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#define REG_BASE_OFFSET 1024
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#define REG_R0 (REG_BASE_OFFSET + (0 * 4))
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#define REG_R1 (REG_BASE_OFFSET + (1 * 4))
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#define REG_R2 (REG_BASE_OFFSET + (2 * 4))
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#define REG_R3 (REG_BASE_OFFSET + (3 * 4))
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#define REG_R4 (REG_BASE_OFFSET + (4 * 4))
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#define REG_R5 (REG_BASE_OFFSET + (5 * 4))
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#define REG_R6 (REG_BASE_OFFSET + (6 * 4))
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#define REG_R7 (REG_BASE_OFFSET + (7 * 4))
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#define REG_R8 (REG_BASE_OFFSET + (8 * 4))
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#define REG_R9 (REG_BASE_OFFSET + (9 * 4))
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#define REG_R10 (REG_BASE_OFFSET + (10 * 4))
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#define REG_R11 (REG_BASE_OFFSET + (11 * 4))
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#define REG_R12 (REG_BASE_OFFSET + (12 * 4))
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#define REG_R13 (REG_BASE_OFFSET + (13 * 4))
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#define REG_R14 (REG_BASE_OFFSET + (14 * 4))
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#define REG_SP (REG_BASE_OFFSET + (13 * 4))
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#define REG_LR (REG_BASE_OFFSET + (14 * 4))
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#define REG_PC (REG_BASE_OFFSET + (15 * 4))
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#define REG_N_FLAG (REG_BASE_OFFSET + (16 * 4))
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#define REG_Z_FLAG (REG_BASE_OFFSET + (17 * 4))
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#define REG_C_FLAG (REG_BASE_OFFSET + (18 * 4))
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#define REG_V_FLAG (REG_BASE_OFFSET + (19 * 4))
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#define REG_CPSR (REG_BASE_OFFSET + (20 * 4))
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#define REG_SAVE (REG_BASE_OFFSET + (21 * 4))
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#define REG_SAVE2 (REG_BASE_OFFSET + (22 * 4))
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#define REG_SAVE3 (REG_BASE_OFFSET + (23 * 4))
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#define CPU_MODE (REG_BASE_OFFSET + (29 * 4))
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#define CPU_HALT_STATE (REG_BASE_OFFSET + (30 * 4))
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#define CHANGED_PC_STATUS (REG_BASE_OFFSET + (31 * 4))
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#define reg_a0 r0
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#define reg_a1 r1
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#define reg_a2 r2
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#define reg_s0 r9
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#define reg_base sp
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#define reg_flags r11
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#define reg_cycles r12
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#define reg_x0 r3
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#define reg_x1 r4
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#define reg_x2 r5
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#define reg_x3 r6
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#define reg_x4 r7
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#define reg_x5 r8
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#define MODE_SUPERVISOR 3
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#ifdef __ARM_ARCH_7A__
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#define extract_u16(rd, rs) \
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uxth rd, rs
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#else
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#define extract_u16(rd, rs) \
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bic rd, rs, #0xff000000 ;\
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bic rd, rd, #0x00ff0000
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#endif
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@ Will load the register set from memory into the appropriate cached registers.
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@ See arm_emit.h for listing explanation.
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#define load_registers_arm() ;\
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ldr reg_x0, [reg_base, #REG_R0] ;\
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ldr reg_x1, [reg_base, #REG_R1] ;\
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ldr reg_x2, [reg_base, #REG_R6] ;\
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ldr reg_x3, [reg_base, #REG_R9] ;\
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ldr reg_x4, [reg_base, #REG_R12] ;\
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ldr reg_x5, [reg_base, #REG_R14] ;\
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#define load_registers_thumb() ;\
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ldr reg_x0, [reg_base, #REG_R0] ;\
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ldr reg_x1, [reg_base, #REG_R1] ;\
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ldr reg_x2, [reg_base, #REG_R2] ;\
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ldr reg_x3, [reg_base, #REG_R3] ;\
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ldr reg_x4, [reg_base, #REG_R4] ;\
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ldr reg_x5, [reg_base, #REG_R5] ;\
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@ Will store the register set from cached registers back to memory.
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#define store_registers_arm() ;\
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str reg_x0, [reg_base, #REG_R0] ;\
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str reg_x1, [reg_base, #REG_R1] ;\
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str reg_x2, [reg_base, #REG_R6] ;\
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str reg_x3, [reg_base, #REG_R9] ;\
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str reg_x4, [reg_base, #REG_R12] ;\
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str reg_x5, [reg_base, #REG_R14] ;\
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#define store_registers_thumb() ;\
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str reg_x0, [reg_base, #REG_R0] ;\
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str reg_x1, [reg_base, #REG_R1] ;\
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str reg_x2, [reg_base, #REG_R2] ;\
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str reg_x3, [reg_base, #REG_R3] ;\
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str reg_x4, [reg_base, #REG_R4] ;\
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str reg_x5, [reg_base, #REG_R5] ;\
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@ Returns an updated persistent cpsr with the cached flags register.
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@ Uses reg as a temporary register and returns the CPSR here.
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#define collapse_flags_no_update(reg) ;\
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ldr reg, [reg_base, #REG_CPSR] /* reg = cpsr */;\
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bic reg, reg, #0xF0000000 /* clear ALU flags in cpsr */;\
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and reg_flags, reg_flags, #0xF0000000 /* clear non-ALU flags */;\
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orr reg, reg, reg_flags /* update cpsr with ALU flags */;\
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@ Updates cpsr using the above macro.
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#define collapse_flags(reg) ;\
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collapse_flags_no_update(reg) ;\
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str reg, [reg_base, #REG_CPSR] ;\
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@ Loads the saved flags register from the persistent cpsr.
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#define extract_flags() ;\
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ldr reg_flags, [reg_base, #REG_CPSR] ;\
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msr cpsr_f, reg_flags ;\
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#define save_flags() ;\
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mrs reg_flags, cpsr ;\
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#define restore_flags() ;\
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msr cpsr_f, reg_flags ;\
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#ifdef __ARM_EABI__
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@ must align stack
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#define call_c_saved_regs r2, r3, r12, lr
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#else
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#define call_c_saved_regs r3, r12, lr
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#endif
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@ Calls a C function - all caller save registers which are important to the
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@ dynarec and to returning from this function are saved.
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#define call_c_function(function) ;\
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stmdb sp!, { call_c_saved_regs } ;\
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bl function ;\
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ldmia sp!, { call_c_saved_regs } ;\
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@ Update the GBA hardware (video, sound, input, etc)
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@ Input:
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@ r0: current PC
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#define return_straight() ;\
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bx lr ;\
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#define return_add() ;\
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add pc, lr, #4 ;\
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#define load_pc_straight() ;\
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ldr r0, [lr, #-8] ;\
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#define load_pc_add() ;\
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ldr r0, [lr] ;\
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#define arm_update_gba_builder(name, mode, return_op) ;\
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;\
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arm_update_gba_##name: ;\
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load_pc_##return_op() ;\
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str r0, [reg_base, #REG_PC] /* write out the PC */;\
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;\
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save_flags() ;\
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collapse_flags(r0) /* update the flags */;\
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;\
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store_registers_##mode() /* save out registers */;\
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call_c_function(update_gba) /* update GBA state */;\
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;\
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mvn reg_cycles, r0 /* load new cycle count */;\
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;\
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ldr r0, [reg_base, #CHANGED_PC_STATUS] /* load PC changed status */;\
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cmp r0, #0 /* see if PC has changed */;\
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beq 1f /* if not return */;\
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;\
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ldr r0, [reg_base, #REG_PC] /* load new PC */;\
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ldr r1, [reg_base, #REG_CPSR] /* r1 = flags */;\
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tst r1, #0x20 /* see if Thumb bit is set */;\
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bne 2f /* if so load Thumb PC */;\
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;\
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load_registers_arm() /* load ARM regs */;\
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call_c_function(block_lookup_address_arm) ;\
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restore_flags() ;\
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bx r0 /* jump to new ARM block */;\
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;\
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1: ;\
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load_registers_##mode() /* reload registers */;\
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restore_flags() ;\
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return_##return_op() ;\
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;\
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2: ;\
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load_registers_thumb() /* load Thumb regs */;\
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call_c_function(block_lookup_address_thumb) ;\
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restore_flags() ;\
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bx r0 /* jump to new ARM block */;\
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arm_update_gba_builder(arm, arm, straight)
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arm_update_gba_builder(thumb, thumb, straight)
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arm_update_gba_builder(idle_arm, arm, add)
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arm_update_gba_builder(idle_thumb, thumb, add)
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@ These are b stubs for performing indirect branches. They are not
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@ linked to and don't return, instead they link elsewhere.
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@ Input:
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@ r0: PC to branch to
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arm_indirect_branch_arm:
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save_flags()
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0
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arm_indirect_branch_thumb:
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save_flags()
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0
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arm_indirect_branch_dual_arm:
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save_flags()
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tst r0, #0x01 @ check lower bit
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bne 1f @ if set going to Thumb mode
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0 @ return
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1:
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bic r0, r0, #0x01
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store_registers_arm() @ save out ARM registers
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load_registers_thumb() @ load in Thumb registers
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ldr r1, [reg_base, #REG_CPSR] @ load cpsr
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orr r1, r1, #0x20 @ set Thumb mode
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str r1, [reg_base, #REG_CPSR] @ store flags
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0 @ return
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arm_indirect_branch_dual_thumb:
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save_flags()
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tst r0, #0x01 @ check lower bit
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beq 1f @ if set going to ARM mode
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bic r0, r0, #0x01
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0 @ return
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1:
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store_registers_thumb() @ save out Thumb registers
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load_registers_arm() @ load in ARM registers
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ldr r1, [reg_base, #REG_CPSR] @ load cpsr
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bic r1, r1, #0x20 @ clear Thumb mode
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str r1, [reg_base, #REG_CPSR] @ store flags
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0 @ return
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@ Update the cpsr.
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@ Input:
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@ r0: new cpsr value
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@ r1: bitmask of which bits in cpsr to update
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@ r2: current PC
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execute_store_cpsr:
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save_flags()
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and reg_flags, r0, r1 @ reg_flags = new_cpsr & store_mask
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ldr r0, [reg_base, #REG_CPSR] @ r0 = cpsr
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bic r0, r0, r1 @ r0 = cpsr & ~store_mask
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orr reg_flags, reg_flags, r0 @ reg_flags = new_cpsr | cpsr
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mov r0, reg_flags @ also put new cpsr in r0
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store_registers_arm() @ save ARM registers
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ldr r2, [lr] @ r2 = pc
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call_c_function(execute_store_cpsr_body)
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load_registers_arm() @ restore ARM registers
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cmp r0, #0 @ check new PC
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beq 1f @ if it's zero, return
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0 @ return to new ARM address
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1:
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restore_flags()
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add pc, lr, #4 @ return
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@ Update the current spsr.
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@ Input:
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@ r0: new cpsr value
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@ r1: bitmask of which bits in spsr to update
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execute_store_spsr:
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ldr r1, =spsr @ r1 = spsr
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ldr r2, [reg_base, #CPU_MODE] @ r2 = CPU_MODE
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str r0, [r1, r2, lsl #2] @ spsr[CPU_MODE] = new_spsr
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bx lr
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@ Read the current spsr.
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@ Output:
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@ r0: spsr
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execute_read_spsr:
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ldr r0, =spsr @ r0 = spsr
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ldr r1, [reg_base, #CPU_MODE] @ r1 = CPU_MODE
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ldr r0, [r0, r1, lsl #2] @ r0 = spsr[CPU_MODE]
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bx lr @ return
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@ Restore the cpsr from the mode spsr and mode shift.
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@ Input:
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@ r0: current pc
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execute_spsr_restore:
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save_flags()
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ldr r1, =spsr @ r1 = spsr
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ldr r2, [reg_base, #CPU_MODE] @ r2 = cpu_mode
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ldr r1, [r1, r2, lsl #2] @ r1 = spsr[cpu_mode] (new cpsr)
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str r1, [reg_base, #REG_CPSR] @ update cpsr
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mov reg_flags, r1 @ also, update shadow flags
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@ This function call will pass r0 (address) and return it.
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store_registers_arm() @ save ARM registers
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call_c_function(execute_spsr_restore_body)
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ldr r1, [reg_base, #REG_CPSR] @ r1 = cpsr
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tst r1, #0x20 @ see if Thumb mode is set
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bne 2f @ if so handle it
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load_registers_arm() @ restore ARM registers
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call_c_function(block_lookup_address_arm)
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restore_flags()
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bx r0
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2:
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load_registers_thumb() @ load Thumb registers
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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bx r0
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@ Setup the mode transition work for calling an SWI.
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@ Input:
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@ r0: current pc
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#define execute_swi_builder(mode) ;\
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;\
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execute_swi_##mode: ;\
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save_flags() ;\
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ldr r1, =reg_mode /* r1 = reg_mode */;\
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/* reg_mode[MODE_SUPERVISOR][6] = pc */;\
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ldr r0, [lr] /* load PC */;\
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str r0, [r1, #((MODE_SUPERVISOR * (7 * 4)) + (6 * 4))] ;\
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collapse_flags_no_update(r0) /* r0 = cpsr */;\
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ldr r1, =spsr /* r1 = spsr */;\
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str r0, [r1, #(MODE_SUPERVISOR * 4)] /* spsr[MODE_SUPERVISOR] = cpsr */;\
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bic r0, r0, #0x3F /* clear mode flag in r0 */;\
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orr r0, r0, #0x13 /* set to supervisor mode */;\
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str r0, [reg_base, #REG_CPSR] /* update cpsr */;\
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;\
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call_c_function(bios_region_read_allow) ;\
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;\
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mov r0, #MODE_SUPERVISOR ;\
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;\
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store_registers_##mode() /* store regs for mode */;\
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call_c_function(set_cpu_mode) /* set the CPU mode to svsr */;\
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load_registers_arm() /* load ARM regs */;\
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;\
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restore_flags() ;\
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add pc, lr, #4 /* return */;\
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execute_swi_builder(arm)
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execute_swi_builder(thumb)
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@ Wrapper for calling SWI functions in C (or can implement some in ASM if
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@ desired)
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#define execute_swi_function_builder(swi_function, mode) ;\
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;\
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.global execute_swi_hle_##swi_function##_##mode ;\
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execute_swi_hle_##swi_function##_##mode: ;\
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save_flags() ;\
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store_registers_##mode() ;\
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call_c_function(execute_swi_hle_##swi_function##_c) ;\
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load_registers_##mode() ;\
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restore_flags() ;\
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bx lr ;\
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execute_swi_function_builder(div, arm)
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execute_swi_function_builder(div, thumb)
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@ Start program execution. Normally the mode should be Thumb and the
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@ PC should be 0x8000000, however if a save state is preloaded this
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@ will be different.
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@ Input:
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@ r0: initial value for cycle counter
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@ Uses sp as reg_base; must hold consistently true.
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execute_arm_translate:
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sub sp, sp, #0x100 @ allocate room for register data
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mvn reg_cycles, r0 @ load cycle counter
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mov r0, reg_base @ load reg_base into first param
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call_c_function(move_reg) @ make reg_base the new reg ptr
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sub sp, sp, #REG_BASE_OFFSET @ allocate room for ptr table
|
|
bl load_ptr_read_function_table @ load read function ptr table
|
|
|
|
ldr r0, [reg_base, #REG_PC] @ r0 = current pc
|
|
ldr r1, [reg_base, #REG_CPSR] @ r1 = flags
|
|
tst r1, #0x20 @ see if Thumb bit is set
|
|
|
|
bne 1f @ if so lookup thumb
|
|
|
|
load_registers_arm() @ load ARM registers
|
|
call_c_function(block_lookup_address_arm)
|
|
extract_flags() @ load flags
|
|
bx r0 @ jump to first ARM block
|
|
|
|
1:
|
|
load_registers_thumb() @ load Thumb registers
|
|
call_c_function(block_lookup_address_thumb)
|
|
extract_flags() @ load flags
|
|
bx r0 @ jump to first Thumb block
|
|
|
|
|
|
@ Write out to memory.
|
|
|
|
@ Input:
|
|
@ r0: address
|
|
@ r1: value
|
|
@ r2: current pc
|
|
|
|
#define execute_store_body(store_type, store_op) ;\
|
|
save_flags() ;\
|
|
stmdb sp!, { lr } /* save lr */;\
|
|
tst r0, #0xF0000000 /* make sure address is in range */;\
|
|
bne ext_store_u##store_type /* if not do ext store */;\
|
|
;\
|
|
ldr r2, =memory_map_write /* r2 = memory_map_write */;\
|
|
mov lr, r0, lsr #15 /* lr = page index of address */;\
|
|
ldr r2, [r2, lr, lsl #2] /* r2 = memory page */;\
|
|
;\
|
|
cmp r2, #0 /* see if map is ext */;\
|
|
beq ext_store_u##store_type /* if so do ext store */;\
|
|
;\
|
|
mov r0, r0, lsl #17 /* isolate bottom 15 bits in top */;\
|
|
mov r0, r0, lsr #17 /* like performing and 0x7FFF */;\
|
|
store_op r1, [r2, r0] /* store result */;\
|
|
|
|
|
|
#define store_align_8() ;\
|
|
and r1, r1, #0xff ;\
|
|
|
|
#define store_align_16() ;\
|
|
bic r0, r0, #0x01 ;\
|
|
extract_u16(r1, r1) ;\
|
|
|
|
#define store_align_32() ;\
|
|
bic r0, r0, #0x03 ;\
|
|
|
|
|
|
#define execute_store_builder(store_type, store_op, load_op) ;\
|
|
;\
|
|
execute_store_u##store_type: ;\
|
|
execute_store_body(store_type, store_op) ;\
|
|
sub r2, r2, #0x8000 /* Pointer to code status data */;\
|
|
load_op r0, [r2, r0] /* check code flag */;\
|
|
;\
|
|
cmp r0, #0 /* see if it's not 0 */;\
|
|
bne 2f /* if so perform smc write */;\
|
|
ldmia sp!, { lr } /* restore lr */;\
|
|
restore_flags() ;\
|
|
add pc, lr, #4 /* return */;\
|
|
;\
|
|
2: ;\
|
|
ldmia sp!, { lr } /* restore lr */;\
|
|
ldr r0, [lr] /* load PC */;\
|
|
str r0, [reg_base, #REG_PC] /* write out PC */;\
|
|
b smc_write /* perform smc write */;\
|
|
;\
|
|
ext_store_u##store_type: ;\
|
|
ldmia sp!, { lr } /* pop lr off of stack */;\
|
|
ldr r2, [lr] /* load PC */;\
|
|
str r2, [reg_base, #REG_PC] /* write out PC */;\
|
|
store_align_##store_type() ;\
|
|
call_c_function(write_memory##store_type) ;\
|
|
b write_epilogue /* handle additional write stuff */;\
|
|
|
|
execute_store_builder(8, strb, ldrb)
|
|
execute_store_builder(16, strh, ldrh)
|
|
execute_store_builder(32, str, ldr)
|
|
|
|
|
|
execute_store_u32_safe:
|
|
execute_store_body(32_safe, str)
|
|
restore_flags()
|
|
ldmia sp!, { pc } @ return
|
|
|
|
ext_store_u32_safe:
|
|
ldmia sp!, { lr } @ Restore lr
|
|
call_c_function(write_memory32) @ Perform 32bit store
|
|
restore_flags()
|
|
bx lr @ Return
|
|
|
|
|
|
write_epilogue:
|
|
cmp r0, #0 @ check if the write rose an alert
|
|
beq 4f @ if not we can exit
|
|
|
|
collapse_flags(r1) @ interrupt needs current flags
|
|
|
|
cmp r0, #2 @ see if the alert is due to SMC
|
|
beq smc_write @ if so, goto SMC handler
|
|
|
|
ldr r1, [reg_base, #REG_CPSR] @ r1 = cpsr
|
|
tst r1, #0x20 @ see if Thumb bit is set
|
|
bne 1f @ if so do Thumb update
|
|
|
|
store_registers_arm() @ save ARM registers
|
|
|
|
3:
|
|
bl update_gba @ update GBA until CPU isn't halted
|
|
|
|
mvn reg_cycles, r0 @ load new cycle count
|
|
ldr r0, [reg_base, #REG_PC] @ load new PC
|
|
ldr r1, [reg_base, #REG_CPSR] @ r1 = flags
|
|
tst r1, #0x20 @ see if Thumb bit is set
|
|
bne 2f
|
|
|
|
load_registers_arm()
|
|
call_c_function(block_lookup_address_arm)
|
|
restore_flags()
|
|
bx r0 @ jump to new ARM block
|
|
|
|
1:
|
|
store_registers_thumb() @ save Thumb registers
|
|
b 3b
|
|
|
|
2:
|
|
load_registers_thumb()
|
|
call_c_function(block_lookup_address_thumb)
|
|
restore_flags()
|
|
bx r0 @ jump to new Thumb block
|
|
|
|
4:
|
|
restore_flags()
|
|
add pc, lr, #4 @ return
|
|
|
|
|
|
smc_write:
|
|
call_c_function(flush_translation_cache_ram)
|
|
|
|
lookup_pc:
|
|
ldr r0, [reg_base, #REG_PC] @ r0 = new pc
|
|
ldr r1, [reg_base, #REG_CPSR] @ r1 = flags
|
|
tst r1, #0x20 @ see if Thumb bit is set
|
|
beq lookup_pc_arm @ if not lookup ARM
|
|
|
|
lookup_pc_thumb:
|
|
call_c_function(block_lookup_address_thumb)
|
|
restore_flags()
|
|
bx r0 @ jump to new Thumb block
|
|
|
|
lookup_pc_arm:
|
|
call_c_function(block_lookup_address_arm)
|
|
restore_flags()
|
|
bx r0 @ jump to new ARM block
|
|
|
|
|
|
#define sign_extend_u8(reg)
|
|
#define sign_extend_u16(reg)
|
|
#define sign_extend_u32(reg)
|
|
|
|
#define sign_extend_s8(reg) ;\
|
|
mov reg, reg, lsl #24 /* shift reg into upper 8bits */;\
|
|
mov reg, reg, asr #24 /* shift down, sign extending */;\
|
|
|
|
#define sign_extend_s16(reg) ;\
|
|
mov reg, reg, lsl #16 /* shift reg into upper 16bits */;\
|
|
mov reg, reg, asr #16 /* shift down, sign extending */;\
|
|
|
|
#define execute_load_op_u8(load_op) ;\
|
|
mov r0, r0, lsl #17 ;\
|
|
load_op r0, [r2, r0, lsr #17] ;\
|
|
|
|
#define execute_load_op_s8(load_op) ;\
|
|
mov r0, r0, lsl #17 ;\
|
|
mov r0, r0, lsr #17 ;\
|
|
load_op r0, [r2, r0] ;\
|
|
|
|
#define execute_load_op_u16(load_op) ;\
|
|
execute_load_op_s8(load_op) ;\
|
|
|
|
#define execute_load_op_s16(load_op) ;\
|
|
execute_load_op_s8(load_op) ;\
|
|
|
|
#define execute_load_op_u16(load_op) ;\
|
|
execute_load_op_s8(load_op) ;\
|
|
|
|
#define execute_load_op_u32(load_op) ;\
|
|
execute_load_op_u8(load_op) ;\
|
|
|
|
|
|
#define execute_load_builder(load_type, load_function, load_op, mask) ;\
|
|
;\
|
|
execute_load_##load_type: ;\
|
|
save_flags() ;\
|
|
tst r0, mask /* make sure address is in range */;\
|
|
bne ext_load_##load_type /* if not do ext load */;\
|
|
;\
|
|
ldr r2, =memory_map_read /* r2 = memory_map_read */;\
|
|
mov r1, r0, lsr #15 /* r1 = page index of address */;\
|
|
ldr r2, [r2, r1, lsl #2] /* r2 = memory page */;\
|
|
;\
|
|
cmp r2, #0 /* see if map is ext */;\
|
|
beq ext_load_##load_type /* if so do ext load */;\
|
|
;\
|
|
execute_load_op_##load_type(load_op) ;\
|
|
restore_flags() ;\
|
|
add pc, lr, #4 /* return */;\
|
|
;\
|
|
ext_load_##load_type: ;\
|
|
ldr r1, [lr] /* r1 = PC */;\
|
|
str r1, [reg_base, #REG_PC] /* update PC */;\
|
|
call_c_function(read_memory##load_function) ;\
|
|
sign_extend_##load_type(r0) /* sign extend result */;\
|
|
restore_flags() ;\
|
|
add pc, lr, #4 /* return */;\
|
|
|
|
|
|
execute_load_builder(u8, 8, ldrneb, #0xF0000000)
|
|
execute_load_builder(s8, 8, ldrnesb, #0xF0000000)
|
|
execute_load_builder(u16, 16, ldrneh, #0xF0000001)
|
|
execute_load_builder(s16, 16_signed, ldrnesh, #0xF0000001)
|
|
execute_load_builder(u32, 32, ldrne, #0xF0000000)
|
|
|
|
|
|
#define execute_ptr_builder(region, ptr, bits) ;\
|
|
;\
|
|
execute_##region##_ptr: ;\
|
|
ldr r1, =(ptr) /* load region ptr */;\
|
|
mov r0, r0, lsl #(32 - bits) /* isolate bottom bits */;\
|
|
mov r0, r0, lsr #(32 - bits) ;\
|
|
bx lr /* return */;\
|
|
|
|
|
|
execute_bios_ptr_protected:
|
|
ldr r1, =bios_read_protect @ load bios read ptr
|
|
and r0, r0, #0x03 @ only want bottom 2 bits
|
|
bx lr @ return
|
|
|
|
|
|
@ address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000;
|
|
|
|
execute_ewram_ptr:
|
|
ldr r1, =(ewram + 0x8000) @ load ewram read ptr
|
|
mov r2, r0, lsl #17 @ isolate bottom 15 bits
|
|
mov r2, r2, lsr #17
|
|
and r0, r0, #0x38000 @ isolate top 2 bits
|
|
add r0, r2, r0, lsl #1 @ add top 2 bits * 2 to bottom 15
|
|
bx lr @ return
|
|
|
|
|
|
@ u32 gamepak_index = address >> 15;
|
|
@ u8 *map = memory_map_read[gamepak_index];
|
|
|
|
@ if(map == NULL)
|
|
@ map = load_gamepak_page(gamepak_index & 0x3FF);
|
|
|
|
@ value = address##type(map, address & 0x7FFF)
|
|
|
|
execute_gamepak_ptr:
|
|
ldr r1, =memory_map_read @ load memory_map_read
|
|
mov r2, r0, lsr #15 @ isolate top 17 bits
|
|
ldr r1, [r1, r2, lsl #2] @ load memory map read ptr
|
|
|
|
save_flags()
|
|
cmp r1, #0 @ see if map entry is NULL
|
|
bne 2f @ if not resume
|
|
|
|
stmdb sp!, { r0 } @ save r0 on stack
|
|
mov r2, r2, lsl #20 @ isolate page index
|
|
mov r0, r2, lsr #20
|
|
call_c_function(load_gamepak_page) @ read new page into r0
|
|
|
|
mov r1, r0 @ new map = return
|
|
ldmia sp!, { r0 } @ restore r0
|
|
|
|
2:
|
|
mov r0, r0, lsl #17 @ isolate bottom 15 bits
|
|
mov r0, r0, lsr #17
|
|
restore_flags()
|
|
bx lr @ return
|
|
|
|
|
|
@ These will store the result in a pointer, then pass that pointer.
|
|
|
|
execute_eeprom_ptr:
|
|
save_flags()
|
|
|
|
call_c_function(read_eeprom) @ load EEPROM result
|
|
add r1, reg_base, #(REG_SAVE & 0xFF00)
|
|
add r1, r1, #(REG_SAVE & 0xFF)
|
|
strh r0, [r1] @ write result out
|
|
mov r0, #0 @ zero out address
|
|
|
|
restore_flags()
|
|
bx lr @ return
|
|
|
|
|
|
execute_backup_ptr:
|
|
save_flags()
|
|
|
|
mov r0, r0, lsl #16 @ only want top 16 bits
|
|
mov r0, r0, lsr #16
|
|
call_c_function(read_backup) @ load backup result
|
|
add r1, reg_base, #(REG_SAVE & 0xFF00)
|
|
add r1, r1, #(REG_SAVE & 0xFF)
|
|
strb r0, [r1] @ write result out
|
|
mov r0, #0 @ zero out address
|
|
|
|
restore_flags()
|
|
bx lr @ return
|
|
|
|
|
|
execute_open_ptr:
|
|
ldr r1, [reg_base, #REG_CPSR] @ r1 = cpsr
|
|
save_flags()
|
|
|
|
stmdb sp!, { r0 } @ save r0
|
|
|
|
ldr r0, [lr, #-4] @ r0 = current PC
|
|
|
|
tst r1, #0x20 @ see if Thumb bit is set
|
|
bne 1f @ if so load Thumb op
|
|
|
|
call_c_function(read_memory32) @ read open address
|
|
|
|
add r1, reg_base, #((REG_SAVE + 4) & 0xFF00)
|
|
add r1, r1, #((REG_SAVE + 4) & 0xFF)
|
|
add r1, r1, reg_base
|
|
str r0, [r1] @ write out
|
|
|
|
ldmia sp!, { r0 } @ restore r0
|
|
and r0, r0, #0x03 @ isolate bottom 2 bits
|
|
|
|
restore_flags()
|
|
bx lr
|
|
|
|
1:
|
|
call_c_function(read_memory16) @ read open address
|
|
|
|
orr r0, r0, r0, lsl #16 @ duplicate opcode over halves
|
|
add r1, reg_base, #((REG_SAVE + 4) & 0xFF00)
|
|
add r1, r1, #((REG_SAVE + 4) & 0xFF)
|
|
|
|
add r1, r1, reg_base
|
|
str r0, [r1] @ write out
|
|
|
|
ldmia sp!, { r0 } @ restore r0
|
|
and r0, r0, #0x03 @ isolate bottom 2 bits
|
|
|
|
restore_flags();
|
|
bx lr
|
|
|
|
|
|
execute_ptr_builder(bios_rom, bios_rom, 14)
|
|
execute_ptr_builder(iwram, iwram + 0x8000, 15)
|
|
execute_ptr_builder(vram, vram, 17)
|
|
execute_ptr_builder(oam_ram, oam_ram, 10)
|
|
execute_ptr_builder(io_registers, io_registers, 10)
|
|
execute_ptr_builder(palette_ram, palette_ram, 10)
|
|
|
|
ptr_read_function_table:
|
|
.word execute_bios_ptr_protected @ 0x00: BIOS
|
|
.word execute_open_ptr @ 0x01: open
|
|
.word execute_ewram_ptr @ 0x02: ewram
|
|
.word execute_iwram_ptr @ 0x03: iwram
|
|
.word execute_io_registers_ptr @ 0x04: I/O registers
|
|
.word execute_palette_ram_ptr @ 0x05: palette RAM
|
|
.word execute_vram_ptr @ 0x06: vram
|
|
.word execute_oam_ram_ptr @ 0x07: oam RAM
|
|
.word execute_gamepak_ptr @ 0x08: gamepak
|
|
.word execute_gamepak_ptr @ 0x09: gamepak
|
|
.word execute_gamepak_ptr @ 0x0A: gamepak
|
|
.word execute_gamepak_ptr @ 0x0B: gamepak
|
|
.word execute_gamepak_ptr @ 0x0C: gamepak
|
|
.word execute_eeprom_ptr @ 0x0D: EEPROM
|
|
.word execute_backup_ptr @ 0x0E: backup
|
|
|
|
.rept (256 - 15) @ 0x0F - 0xFF: open
|
|
.word execute_open_ptr
|
|
.endr
|
|
|
|
|
|
@ Setup the read function table.
|
|
@ Load this onto the the stack; assume we're free to use r3
|
|
|
|
load_ptr_read_function_table:
|
|
mov r0, #256 @ 256 elements
|
|
ldr r1, =ptr_read_function_table @ r0 = ptr_read_function_table
|
|
mov r2, sp @ load here
|
|
|
|
2:
|
|
ldr r3, [r1], #4 @ read pointer
|
|
str r3, [r2], #4 @ write pointer
|
|
|
|
subs r0, r0, #1 @ goto next iteration
|
|
bne 2b
|
|
|
|
bx lr
|
|
|
|
|
|
@ Patch the read function table to allow for BIOS reads.
|
|
|
|
execute_patch_bios_read:
|
|
ldr r1, =reg @ r1 = reg
|
|
ldr r0, =execute_bios_rom_ptr @ r0 = patch function
|
|
ldr r1, [r1]
|
|
str r0, [r1, #-REG_BASE_OFFSET]
|
|
bx lr
|
|
|
|
|
|
@ Patch the read function table to allow for BIOS reads.
|
|
|
|
execute_patch_bios_protect:
|
|
ldr r1, =reg @ r1 = reg
|
|
ldr r0, =execute_bios_ptr_protected @ r0 = patch function
|
|
ldr r1, [r1]
|
|
str r0, [r1, #-REG_BASE_OFFSET]
|
|
bx lr
|
|
|
|
|
|
#define save_reg_scratch(reg) ;\
|
|
ldr r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4))] ;\
|
|
str r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4) + 128)] ;\
|
|
|
|
#define restore_reg_scratch(reg) ;\
|
|
ldr r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4) + 128)] ;\
|
|
str r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4))] ;\
|
|
|
|
#define scratch_regs_thumb(type) ;\
|
|
type##_reg_scratch(0) ;\
|
|
type##_reg_scratch(1) ;\
|
|
type##_reg_scratch(2) ;\
|
|
type##_reg_scratch(3) ;\
|
|
type##_reg_scratch(4) ;\
|
|
type##_reg_scratch(5) ;\
|
|
|
|
#define scratch_regs_arm(type) ;\
|
|
type##_reg_scratch(0) ;\
|
|
type##_reg_scratch(1) ;\
|
|
type##_reg_scratch(6) ;\
|
|
type##_reg_scratch(9) ;\
|
|
type##_reg_scratch(12) ;\
|
|
type##_reg_scratch(14) ;\
|
|
|
|
|
|
step_debug_arm:
|
|
save_flags()
|
|
collapse_flags(r0)
|
|
|
|
ldr r0, [reg_base, #REG_CPSR] @ r1 = cpsr
|
|
tst r0, #0x20 @ see if Thumb bit is set
|
|
|
|
ldr r0, [lr] @ load PC
|
|
mvn r1, reg_cycles @ load cycle counter
|
|
|
|
beq 1f @ if not goto ARM mode
|
|
|
|
scratch_regs_thumb(save)
|
|
|
|
store_registers_thumb() @ write back Thumb regs
|
|
call_c_function(step_debug) @ call debug step
|
|
scratch_regs_thumb(restore)
|
|
restore_flags()
|
|
add pc, lr, #4 @ return
|
|
|
|
1:
|
|
scratch_regs_arm(save)
|
|
store_registers_arm() @ write back ARM regs
|
|
call_c_function(step_debug) @ call debug step
|
|
scratch_regs_arm(restore)
|
|
restore_flags()
|
|
add pc, lr, #4 @ return, skipping PC
|
|
|
|
.pool
|
|
|
|
.comm memory_map_read 0x8000
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.comm memory_map_write 0x8000
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