633 lines
17 KiB
ArmAsm
633 lines
17 KiB
ArmAsm
# gameplaySP
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#
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# Copyright (C) 2006 Exophase <exophase@gmail.com>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#include "../gpsp_config.h"
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// This is also defined in sys/asm.h but doesn't seem portable?
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#ifdef __mips64
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.set mips64
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#define SZREG 8
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#define REG_L ld
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#define REG_S sd
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#else
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.set mips32r2
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#define SZREG 4
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#define REG_L lw
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#define REG_S sw
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#endif
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#define defsymbl(symbol) \
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.type symbol, %function ;\
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.global symbol ; \
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symbol:
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#define defobj(symbol) \
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.type symbol, %object ;\
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.global symbol ; \
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symbol:
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.align 4
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# MIPS register layout:
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# $0 - constant zero
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# $1 - temporary
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# $2 - temporary / return value
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# $3 - ARM r0 (not saved)
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# $4 - temporary / function argument 0
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# $5 - temporary / function argument 1
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# $6 - temporary / function argument 2
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# $7 - ARM r1 (not saved)
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# $8 - ARM r2 (not saved)
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# $9 - ARM r3 (not saved)
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# $10 - ARM r4 (not saved)
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# $11 - ARM r5 (not saved)
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# $12 - ARM r6 (not saved)
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# $13 - ARM r7 (not saved)
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# $14 - ARM r8 (not saved)
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# $15 - ARM r9 (not saved)
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# $16 - ARM machine state pointer (saved)
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# $17 - cycle counter (saved)
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# $18 - ARM r10 (saved)
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# $19 - block start address (roughly r15) (saved)
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# $20 - ARM negative register (saved)
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# $21 - ARM zero register (saved)
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# $22 - ARM carry register (saved)
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# $23 - ARM overflow register (saved)
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# $24 - ARM r11 (not saved)
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# $25 - ARM r12 (not saved)
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# $26 - kernel temporary 0
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# $27 - kernel temporary 1
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# $28 - ARM r13 (saved)
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# $29 - stack pointer
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# $30 - ARM r14 (saved)
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# $31 - return address
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.equ REG_R0, (0 * 4)
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.equ REG_R1, (1 * 4)
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.equ REG_R2, (2 * 4)
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.equ REG_R3, (3 * 4)
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.equ REG_R4, (4 * 4)
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.equ REG_R5, (5 * 4)
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.equ REG_R6, (6 * 4)
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.equ REG_R7, (7 * 4)
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.equ REG_R8, (8 * 4)
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.equ REG_R9, (9 * 4)
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.equ REG_R10, (10 * 4)
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.equ REG_R11, (11 * 4)
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.equ REG_R12, (12 * 4)
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.equ REG_R13, (13 * 4)
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.equ REG_R14, (14 * 4)
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.equ REG_PC, (15 * 4)
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.equ REG_CPSR, (16 * 4)
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.equ CPU_MODE, (17 * 4)
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.equ CPU_HALT_STATE, (18 * 4)
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.equ REG_BUS_VALUE, (19 * 4)
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.equ REG_N_FLAG, (20 * 4)
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.equ REG_Z_FLAG, (21 * 4)
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.equ REG_C_FLAG, (22 * 4)
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.equ REG_V_FLAG, (23 * 4)
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.equ REG_SLEEP_CYCLES, (24 * 4)
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.equ OAM_UPDATED, (25 * 4)
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.equ REG_SAVE, (26 * 4)
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.equ REG_SAVE2, (27 * 4)
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.equ REG_SAVE3, (28 * 4)
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.equ REG_SAVE4, (29 * 4)
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.equ GP_SAVE, (30 * 4)
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.equ GP_SAVE_HI, (31 * 4)
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.equ CPU_ALERT_HALT, (1 << 0)
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.equ CPU_ALERT_SMC, (1 << 1)
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.equ CPU_ALERT_IRQ, (1 << 2)
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.equ SPSR_BASE, (0x100 + 0x400 * 3)
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.equ REGMODE_BASE, (SPSR_BASE + 24)
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.equ SUPERVISOR_MODE, (0x13)
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.equ SUPERVISOR_SPSR, (3 * 4 + SPSR_BASE)
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.equ SUPERVISOR_LR, ((3 * (7 * 4)) + (6 * 4) + REGMODE_BASE)
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.equ FNPTRS_MEMOPS, (REGMODE_BASE + 196)
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.equ FNPTRS_BASE, (FNPTRS_MEMOPS + 960*2)
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#define reg_cycles $17
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.set noat
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.set noreorder
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# make sure $16 has the register base for these macros
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#ifdef MIPS_HAS_R2_INSTS
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.macro collapse_flag flag_reg, shift
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ins $2, $\flag_reg, \shift, 1 # insert flag into CPSR
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.endm
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.macro extract_flag shift, flag_reg
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ext $\flag_reg, $1, \shift, 1 # extract flag from CPSR
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.endm
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#else
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.macro collapse_flag flag_reg, shift
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sll $1, $\flag_reg, \shift
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or $2, $2, $1
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.endm
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.macro extract_flag shift, flag_reg
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srl $\flag_reg, $1, \shift
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andi $\flag_reg, $\flag_reg, 1
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.endm
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#endif
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.macro collapse_flags
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lw $2, REG_CPSR($16) # load CPSR
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andi $2, $2, 0xFF # isolate lower 8bits
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collapse_flag 20, 31 # store flags
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collapse_flag 21, 30
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collapse_flag 22, 29
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collapse_flag 23, 28
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sw $2, REG_CPSR($16) # store CPSR
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.endm
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.macro extract_flags_body # extract flags from $1
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extract_flag 31, 20 # load flags
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extract_flag 30, 21
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extract_flag 29, 22
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extract_flag 28, 23
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.endm
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.macro extract_flags
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lw $1, REG_CPSR($16) # load CPSR
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extract_flags_body
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.endm
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.macro save_registers
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sw $3, REG_R0($16)
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sw $7, REG_R1($16)
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sw $8, REG_R2($16)
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sw $9, REG_R3($16)
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sw $10, REG_R4($16)
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sw $11, REG_R5($16)
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sw $12, REG_R6($16)
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sw $13, REG_R7($16)
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sw $14, REG_R8($16)
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sw $15, REG_R9($16)
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sw $24, REG_R11($16)
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sw $25, REG_R12($16)
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sw $18, REG_R10($16)
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sw $28, REG_R13($16)
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sw $30, REG_R14($16)
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.endm
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.macro restore_registers
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lw $3, REG_R0($16)
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lw $7, REG_R1($16)
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lw $8, REG_R2($16)
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lw $9, REG_R3($16)
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lw $10, REG_R4($16)
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lw $11, REG_R5($16)
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lw $12, REG_R6($16)
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lw $13, REG_R7($16)
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lw $14, REG_R8($16)
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lw $15, REG_R9($16)
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lw $24, REG_R11($16)
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lw $25, REG_R12($16)
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lw $18, REG_R10($16)
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lw $28, REG_R13($16)
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lw $30, REG_R14($16)
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.endm
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# PIC ABI mandates to jump to target via $t9
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#ifdef PIC
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.macro cfncall target, targetid
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lw $t9, (FNPTRS_BASE + \targetid * 4)($16)
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jalr $t9
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REG_L $28, GP_SAVE($16)
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.endm
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#else
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.macro cfncall target, targetid
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jal \target
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REG_L $28, GP_SAVE($16)
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.endm
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#endif
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# Process a hardware event. Since an interrupt might be
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# raised we have to check if the PC has changed.
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# $4: next address
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# $16: register base
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# $17: cycle counter
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.balign 64
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# This gets called every time the cycle counter runs out
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# (checked at every branch/jump)
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defsymbl(mips_update_gba)
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sw $4, REG_PC($16) # current PC = $4
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sw $ra, REG_SAVE2($16) # save return addr
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collapse_flags # update cpsr
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save_registers # save registers
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move $4, reg_cycles # Remaining cycles as asg0
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cfncall update_gba, 0 # process the next event
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bltz $2, return_to_main # Exit if a frame is complete (bit 31 is set)
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and reg_cycles, $2, 0x7FFF # update new cycle count (ret value)
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sll $1, $2, 1 # Check bit 30 now (PC changed)
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bltz $1, lookup_pc
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lw $ra, REG_SAVE2($16) # restore return address
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restore_registers
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jr $ra # if not, go back to caller
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nop
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# Processes cheats whenever we hit the master PC
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defsymbl(mips_cheat_hook)
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sw $ra, REG_SAVE2($16)
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save_registers
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cfncall process_cheats, 8
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lw $ra, REG_SAVE2($16)
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restore_registers
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jr $ra
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nop
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# Loads the main context and returns to it.
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# ARM regs must be saved before branching here
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return_to_main:
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REG_L $28, GP_SAVE($16) # Restore previous state
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REG_L $s0, 4*SZREG($sp)
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REG_L $s1, 5*SZREG($sp)
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REG_L $s2, 6*SZREG($sp)
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REG_L $s3, 7*SZREG($sp)
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REG_L $s4, 8*SZREG($sp)
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REG_L $s5, 9*SZREG($sp)
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REG_L $s6, 10*SZREG($sp)
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REG_L $s7, 11*SZREG($sp)
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REG_L $fp, 12*SZREG($sp)
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REG_L $ra, 13*SZREG($sp)
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jr $ra # Return to main
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addiu $sp, $sp, 112 # Restore stack pointer (delay slot)
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# Perform an indirect branch.
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# $4: GBA address to branch to
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defsymbl(mips_indirect_branch_arm)
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save_registers
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cfncall block_lookup_address_arm, 1
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restore_registers
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jr $2 # $2 = value returned
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nop
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defsymbl(mips_indirect_branch_thumb)
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save_registers
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cfncall block_lookup_address_thumb, 2
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restore_registers
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jr $2 # $2 = value returned
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nop
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defsymbl(mips_indirect_branch_dual)
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save_registers
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cfncall block_lookup_address_dual, 3
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nop
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restore_registers
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jr $2 # $2 = value returned
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nop
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# Called on I/O writes that have side-effects
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defsymbl(write_io_epilogue)
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# Check for SMC, IRQ, and HALT bits
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move $19, $2 # destroy $19 (saved ~reg_pc) since we won't return
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collapse_flags # CPSR needs to be updated
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andi $4, $19, CPU_ALERT_SMC # check if SMC code happened
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beqz $4, 1f # skip if no SMC happened
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nop
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cfncall flush_translation_cache_ram, 4
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1:
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andi $4, $19, CPU_ALERT_IRQ # check if IRQ was raised
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beqz $4, 2f # skip if no IRQ was raised
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nop
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cfncall check_and_raise_interrupts, 9
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2:
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andi $4, $19, CPU_ALERT_HALT # check if CPU is halted
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beqz $4, lookup_pc # continue running if not halted
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# Purposely fallthrough to cpu_sleep_loop, wait for CPU wakeup
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cpu_sleep_loop:
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move $4, reg_cycles # Remaining cycles as asg0
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cfncall update_gba, 0 # process the next event
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bltz $2, return_to_main # Exit if a frame is complete (bit 31 is set)
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# since no frame was completed, this means CPU is active again.
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# Fall through to lookup_pc to resume execution
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and reg_cycles, $2, 0x7FFF # update new cycle count (ret value)
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lookup_pc:
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extract_flags # $1 contains CPSR now
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lookup_pc_noflags:
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andi $1, $1, 0x20 # isolate mode bit
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beq $1, $0, 1f # if T bit is zero use arm handler
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lw $4, REG_PC($16) # load PC as arg 0
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cfncall block_lookup_address_thumb, 2 # get Thumb address
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restore_registers
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jr $2 # jump to result
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nop
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1:
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cfncall block_lookup_address_arm, 1 # get ARM address
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restore_registers
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jr $2 # jump to result
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nop
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defsymbl(smc_write)
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sw $6, REG_PC($16) # save PC
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save_registers
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cfncall flush_translation_cache_ram, 4
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b lookup_pc_noflags
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lw $1, REG_CPSR($16) # (delay)
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# Return the current cpsr
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defsymbl(execute_read_cpsr)
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collapse_flags # fold flags into cpsr, put cpsr into $2
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jr $ra # return
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nop
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# Return the current spsr
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defsymbl(execute_read_spsr)
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lw $1, CPU_MODE($16) # $1 = cpu_mode
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andi $1, $1, 0xF # remove privilege bits
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sll $1, $1, 2 # adjust to word offset size
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addu $2, $1, $16
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jr $ra # return
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lw $2, SPSR_BASE($2) # $2 = spsr[cpu_mode] (delay slot)
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# Switch into SWI, has to collapse flags
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# $4: Current pc
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defsymbl(execute_swi)
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sw $ra, REG_SAVE3($16)
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sw $4, SUPERVISOR_LR($16) # store next PC in the supervisor's LR
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collapse_flags # get cpsr in $2
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sw $2, SUPERVISOR_SPSR($16) # save cpsr in SUPERVISOR_CPSR
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srl $2, $2, 6 # zero out bottom 6 bits of CPSR
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sll $2, $2, 6
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ori $2, (0x13 | 0x80) # mode supervisor + disable IRQs
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sw $2, REG_CPSR($16) # write back CPSR
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save_registers
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li $4, SUPERVISOR_MODE
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cfncall set_cpu_mode, 5 # set the CPU mode to supervisor
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lw $ra, REG_SAVE3($16)
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restore_registers
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la $2, 0xe3a02004 # Update open BUS value
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jr $ra # return
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sw $2, REG_BUS_VALUE($16)
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# $4: pc to restore to
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# returns in $4
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defsymbl(execute_spsr_restore)
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lw $1, CPU_MODE($16) # $1 = cpu_mode
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andi $1, $1, 0xF # Remove privilege bits
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beq $1, $0, no_spsr_restore # only restore if the cpu isn't user/sys mode
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sll $2, $1, 2 # adjust to word offset size (delay)
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addu $2, $2, $16
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lw $1, SPSR_BASE($2) # $1 = spsr[cpu_mode]
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sw $1, REG_CPSR($16) # cpsr = spsr[cpu_mode]
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extract_flags_body # extract flags from $1
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sw $ra, REG_SAVE3($16)
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save_registers
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cfncall execute_spsr_restore_body, 6 # do the dirty work in this C function
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restore_registers
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lw $ra, REG_SAVE3($16)
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jr $ra
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addu $4, $2, $0 # move return value to $4
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no_spsr_restore:
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jr $ra
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nop
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# $4: new cpsr
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# $5: current PC
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# [ra]: store mask (user)
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# [ra+4]: store mask (privileged)
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defsymbl(execute_store_cpsr)
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lw $6, CPU_MODE($16) # $6 = cpu_mode
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andi $6, $6, 0x10 # Get privilege bit
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srl $6, $6, 2 # Calculate offset
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addu $6, $6, $ra
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lw $6, ($6) # Load mask
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addu $ra, $ra, 8 # Real return address
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and $1, $4, $6 # $1 = new_cpsr & store_mask
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lw $2, REG_CPSR($16) # $2 = current cpsr
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nor $4, $6, $0 # $4 = ~store_mask
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and $2, $2, $4 # $2 = (cpsr & (~store_mask))
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or $1, $1, $2 # $1 = new cpsr combined with old
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extract_flags_body # extract flags from $1
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andi $6, $6, 0xff # Check whether we overwrote mode
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bnez $6, 1f
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sw $1, REG_CPSR($16) # Store new CPSR (delay slot)
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jr $ra
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nop
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1:
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sw $ra, REG_SAVE3($16)
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save_registers
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addu $4, $1, $0 # load the new CPSR
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cfncall execute_store_cpsr_body, 7 # do the dirty work in this C function
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bnez $2, 2f # this could have changed the pc
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nop
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restore_registers
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lw $ra, REG_SAVE3($16)
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jr $ra
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nop
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2:
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addu $4, $2, $0 # load new address in $4
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cfncall block_lookup_address_arm, 1 # GBA address is in $4
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restore_registers # restore registers
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jr $2 # jump to the new address
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nop
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# $4: new spsr
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# $5: store mask
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defsymbl(execute_store_spsr)
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lw $1, CPU_MODE($16) # $1 = cpu_mode
|
|
andi $1, $1, 0xF # Remove privilege bits
|
|
sll $1, $1, 2 # adjust to word offset size
|
|
addu $1, $1, $16
|
|
lw $2, SPSR_BASE($1) # $2 = spsr[cpu_mode]
|
|
and $4, $4, $5 # $4 = new_spsr & store_mask
|
|
nor $5, $5, $0 # $5 = ~store_mask
|
|
and $2, $2, $5 # $2 = (spsr & (~store_mask))
|
|
or $4, $4, $2 # $4 = new spsr combined with old
|
|
jr $ra # return
|
|
sw $4, SPSR_BASE($1) # spsr[cpu_mode] = $4 (delay slot)
|
|
|
|
|
|
# $4: cycle counter argument
|
|
# $5: pointer to reg
|
|
|
|
defsymbl(execute_arm_translate_internal)
|
|
|
|
addiu $sp, $sp, -112 # Store the main thread context
|
|
REG_S $s0, 4*SZREG($sp)
|
|
REG_S $s1, 5*SZREG($sp)
|
|
REG_S $s2, 6*SZREG($sp)
|
|
REG_S $s3, 7*SZREG($sp)
|
|
REG_S $s4, 8*SZREG($sp)
|
|
REG_S $s5, 9*SZREG($sp)
|
|
REG_S $s6, 10*SZREG($sp)
|
|
REG_S $s7, 11*SZREG($sp)
|
|
REG_S $fp, 12*SZREG($sp)
|
|
REG_S $ra, 13*SZREG($sp)
|
|
|
|
move $16, $5
|
|
REG_S $28, GP_SAVE($16)
|
|
|
|
move reg_cycles, $4 # load cycle counter register
|
|
|
|
extract_flags # load flag variables
|
|
|
|
# CPU might be sleeping, do not wake ip up!
|
|
lw $1, CPU_HALT_STATE($16) # check if CPU is sleeping
|
|
bne $1, $0, cpu_sleep_loop # see if it hasn't changed
|
|
|
|
lw $1, REG_CPSR($16)
|
|
and $1, $1, 0x20 # see if Thumb bit is set in flags
|
|
|
|
bne $1, $0, 1f
|
|
lw $4, REG_PC($16) # load PC into $4 (delay)
|
|
|
|
cfncall block_lookup_address_arm, 1
|
|
restore_registers # load initial register values
|
|
jr $2 # jump to return
|
|
nop
|
|
|
|
1:
|
|
cfncall block_lookup_address_thumb, 2
|
|
restore_registers # load initial register values
|
|
jr $2 # jump to return
|
|
nop
|
|
|
|
.bss
|
|
.align 6
|
|
|
|
# Ensure iwram+0x8000 and ewram addresses have identical 31..16 bits
|
|
# We place them at 128KB offset to ensure so.
|
|
defsymbl(iwram)
|
|
.space 0x10000
|
|
defsymbl(vram)
|
|
.space 0x18000
|
|
defsymbl(ewram)
|
|
.space 0x80000
|
|
defsymbl(io_registers)
|
|
.space 0x400
|
|
|
|
.data
|
|
.align 6
|
|
|
|
defobj(memory_map_read)
|
|
.space 0x8000
|
|
|
|
# memory_map_read is immediately before arm_reg on purpose (offset used
|
|
# to access it, via lw op). We do not use write though.
|
|
defobj(reg)
|
|
.space 0x100
|
|
|
|
# Placed here for easy access
|
|
defobj(palette_ram)
|
|
.space 0x400
|
|
defobj(palette_ram_converted)
|
|
.space 0x400
|
|
defobj(oam_ram)
|
|
.space 0x400
|
|
defobj(spsr)
|
|
.space 24 # u32[6]
|
|
defobj(reg_mode)
|
|
.space 196 # u32[7][7];
|
|
|
|
# Here we store:
|
|
# void *tmemld[11][16]; # 10 types of loads
|
|
# void *tmemst[ 4][16]; # 3 types of stores
|
|
# Essentially a list of pointers to the different mem load handlers
|
|
# Keep them close for a fast patcher.
|
|
defobj(tmemld)
|
|
.space 704
|
|
defobj(tmemst)
|
|
.space 256
|
|
defobj(thnjal)
|
|
.space 960
|
|
fnptrs:
|
|
.long update_gba # 0
|
|
.long block_lookup_address_arm # 1
|
|
.long block_lookup_address_thumb # 2
|
|
.long block_lookup_address_dual # 3
|
|
.long flush_translation_cache_ram # 4
|
|
.long set_cpu_mode # 5
|
|
.long execute_spsr_restore_body # 6
|
|
.long execute_store_cpsr_body # 7
|
|
.long process_cheats # 8
|
|
.long check_and_raise_interrupts # 9
|
|
|
|
#if !defined(MMAP_JIT_CACHE)
|
|
|
|
# Make this section executable!
|
|
.text
|
|
#if defined(PSP) || defined(PS2) || defined(NINTENDO64)
|
|
.section .bss
|
|
#else
|
|
# Need to mark the section as awx (for Linux)
|
|
.section .jit,"awx",%nobits
|
|
#endif
|
|
.align 2
|
|
|
|
defsymbl(rom_translation_cache)
|
|
.space ROM_TRANSLATION_CACHE_SIZE
|
|
defsymbl(ram_translation_cache)
|
|
.space RAM_TRANSLATION_CACHE_SIZE
|
|
|
|
#endif
|
|
|