298 lines
14 KiB
C
298 lines
14 KiB
C
/* gameplaySP
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*
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* Copyright (C) 2021 David Guillen Fandos <david@davidgf.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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typedef enum
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{
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aa64_opcode_logic = 0x0A,
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aa64_opcode_addsub = 0x0B,
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aa64_opcode_adr = 0x10,
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aa64_opcode_addsubi = 0x11,
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aa64_opcode_movi = 0x12,
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aa64_opcode_bfm = 0x13,
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aa64_opcode_b = 0x14,
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aa64_opcode_b2 = 0x15,
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aa64_opcode_tbz = 0x16,
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aa64_opcode_tbnz = 0x17,
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aa64_opcode_memi = 0x19,
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aa64_opcode_misc = 0x1A,
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aa64_opcode_mul4 = 0x1B,
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} aa64_opcode;
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typedef enum
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{
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ccode_eq = 0x0, /* Equal Z == 1 */
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ccode_ne = 0x1, /* Not Equal Z == 0 */
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ccode_hs = 0x2, /* Carry Set C == 1 */
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ccode_lo = 0x3, /* Carry Clear C == 0 */
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ccode_mi = 0x4, /* Minus/Neg N == 1 */
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ccode_pl = 0x5, /* Plus/Pos N == 0 */
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ccode_vs = 0x6, /* Overflow V == 1 */
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ccode_vc = 0x7, /* !Overflow V == 0 */
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ccode_hi = 0x8, /* UGreatThan C && !Z */
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ccode_ls = 0x9, /* ULessEqual !C || Z */
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ccode_ge = 0xA, /* SGreatEqual N == V */
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ccode_lt = 0xB, /* SLessThan N != V */
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ccode_gt = 0xC, /* SLessThan !Z&N==V */
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ccode_le = 0xD, /* SLessEqual Z|(N!=V) */
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ccode_al = 0xE, /* Always */
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ccode_nv = 0xF, /* Never */
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} aa64_condcode;
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#define aa64_br_offset(label) \
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(((uintptr_t)(label) - (uintptr_t)(translation_ptr)) >> 2) \
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#define aa64_br_offset_from(label, from) \
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(((uintptr_t)(label) - (uintptr_t)(from)) >> 2) \
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#define aa64_emit_inst(opcode, ope, rd, rs, extra) \
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{ \
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*((u32 *)translation_ptr) = (aa64_opcode_##opcode << 24) | ((ope) << 29) | \
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((rs) << 5) | (rd) | (extra); \
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translation_ptr += 4; \
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}
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#define aa64_emit_ldr(rv, rb, offset) \
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aa64_emit_inst(memi, 5, rv, rb, (1 << 22) | ((offset) << 10)) \
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#define aa64_emit_str(rv, rb, offset) \
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aa64_emit_inst(memi, 5, rv, rb, (0 << 22) | ((offset) << 10)) \
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#define aa64_emit_addshift(rd, rs, rm, st, sa) \
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aa64_emit_inst(addsub, 0, rd, rs, ((rm) << 16) | ((st)<<22) | ((sa)<<10)) \
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#define aa64_emit_add_lsl(rd, rs, rm, sa) \
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aa64_emit_addshift(rd, rs, rm, 0, sa) \
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#define aa64_emit_addi(rd, rs, imm) \
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aa64_emit_inst(addsubi, 0, rd, rs, (imm) << 10) \
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#define aa64_emit_addi12(rd, rs, imm) \
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aa64_emit_inst(addsubi, 0, rd, rs, ((imm) << 10) | (1 << 22)) \
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#define aa64_emit_addis(rd, rs, imm) \
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aa64_emit_inst(addsubi, 1, rd, rs, (imm) << 10) \
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#define aa64_emit_subi(rd, rs, imm) \
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aa64_emit_inst(addsubi, 2, rd, rs, (imm) << 10) \
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#define aa64_emit_subi12(rd, rs, imm) \
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aa64_emit_inst(addsubi, 2, rd, rs, ((imm) << 10) | (1 << 22)) \
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#define aa64_emit_subis(rd, rs, imm) \
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aa64_emit_inst(addsubi, 3, rd, rs, (imm) << 10) \
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/* rd = ra + rn * rm */
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#define aa64_emit_madd(rd, ra, rn, rm) \
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aa64_emit_inst(mul4, 0, rd, rn, ((ra) << 10) | ((rm) << 16)) \
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/* rd = ra - rn * rm */
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#define aa64_emit_msub(rd, ra, rn, rm) \
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aa64_emit_inst(mul4, 0, rd, rn, ((ra) << 10) | ((rm) << 16) | 0x8000) \
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#define aa64_emit_smaddl(rd, ra, rn, rm) \
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aa64_emit_inst(mul4, 4, rd, rn, ((ra) << 10) | ((rm) << 16) | 0x200000) \
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#define aa64_emit_umaddl(rd, ra, rn, rm) \
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aa64_emit_inst(mul4, 4, rd, rn, ((ra) << 10) | ((rm) << 16) | 0xA00000) \
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#define aa64_emit_mul(rd, rn, rm) \
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aa64_emit_madd(rd, 31, rn, rm) \
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// MovZ, clears the highest bits and sets the lower ones
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#define aa64_emit_movlo(rd, imm) \
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aa64_emit_inst(movi, 2, rd, 0, (((imm) & 0xffff) << 5) | (4 << 21)) \
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// MovZ, clears the lowest bits and sets the higher ones
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#define aa64_emit_movhiz(rd, imm) \
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aa64_emit_inst(movi, 2, rd, 0, (((imm) & 0xffff) << 5) | (5 << 21)) \
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// MovK, keeps the other (lower) bits
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#define aa64_emit_movhi(rd, imm) \
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aa64_emit_inst(movi, 3, rd, 0, (((imm) & 0xffff) << 5) | (5 << 21)) \
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// MovN, moves the inverted immediate (for negative numbers)
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#define aa64_emit_movne(rd, imm) \
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aa64_emit_inst(movi, 0, rd, 0, (((imm) & 0xffff) << 5) | (4 << 21)) \
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#define aa64_emit_branch(offset) \
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aa64_emit_inst(b, 0, 0, 0, (((u32)(offset))) & 0x3ffffff) \
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#define aa64_emit_branch_patch(ptr, offset) \
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*(ptr) = (((*(ptr)) & 0xfc000000) | (((u32)(offset)) & 0x3ffffff)) \
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#define aa64_emit_brcond(cond, offset) \
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aa64_emit_inst(b, 2, cond, 0, ((((u32)(offset))) & 0x7ffff) << 5) \
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#define aa64_emit_brcond_patch(ptr, offset) \
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*(ptr) = (((*(ptr)) & 0xff00001f) | (((((u32)(offset))) & 0x7ffff) << 5)) \
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#define aa64_emit_brlink(offset) \
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aa64_emit_inst(b, 4, 0, 0, (((u32)(offset))) & 0x3ffffff) \
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#define aa64_emit_extr(rd, rs, rm, amount) \
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aa64_emit_inst(bfm, 0, rd, rs, (1 << 23) | ((amount) << 10) | ((rm) << 16)) \
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#define aa64_emit_ror(rd, rs, amount) \
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aa64_emit_extr(rd, rs, rs, amount) \
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#define aa64_emit_lsr(rd, rs, amount) \
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aa64_emit_inst(bfm, 2, rd, rs, (31 << 10) | ((amount) << 16)) \
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#define aa64_emit_lsl(rd, rs, amount) \
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aa64_emit_inst(bfm, 2, rd, rs, ((31-(amount)) << 10) | (((32-(amount)) & 31) << 16))
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#define aa64_emit_asr(rd, rs, amount) \
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aa64_emit_inst(bfm, 0, rd, rs, (31 << 10) | ((amount) << 16)) \
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#define aa64_emit_lsr64(rd, rs, amount) \
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aa64_emit_inst(bfm, 6, rd, rs, (1 << 22) | (63 << 10) | ((amount) << 16)) \
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#define aa64_emit_eori(rd, rs, immr, imms) \
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aa64_emit_inst(movi, 2, rd, rs, ((imms) << 10) | ((immr) << 16)) \
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#define aa64_emit_orri(rd, rs, immr, imms) \
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aa64_emit_inst(movi, 1, rd, rs, ((imms) << 10) | ((immr) << 16)) \
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#define aa64_emit_andi(rd, rs, immr, imms) \
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aa64_emit_inst(movi, 0, rd, rs, ((imms) << 10) | ((immr) << 16)) \
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#define aa64_emit_andi64(rd, rs, immr, imms) \
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aa64_emit_inst(movi, 4, rd, rs, (1 << 22) | ((imms) << 10) | ((immr) << 16))
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#define aa64_emit_mov(rd, rs) \
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aa64_emit_orr(rd, 31, rs) \
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#define aa64_emit_orr(rd, rs, rm) \
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aa64_emit_inst(logic, 1, rd, rs, ((rm) << 16)) \
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#define aa64_emit_orn(rd, rs, rm) \
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aa64_emit_inst(logic, 1, rd, rs, ((rm) << 16) | (1 << 21)) \
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#define aa64_emit_and(rd, rs, rm) \
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aa64_emit_inst(logic, 0, rd, rs, ((rm) << 16)) \
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#define aa64_emit_ands(rd, rs, rm) \
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aa64_emit_inst(logic, 3, rd, rs, ((rm) << 16)) \
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#define aa64_emit_tst(rs, rm) \
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aa64_emit_ands(31, rs, rm) \
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#define aa64_emit_cmpi(rs, imm) \
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aa64_emit_subis(31, rs, imm) \
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#define aa64_emit_xor(rd, rs, rm) \
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aa64_emit_inst(logic, 2, rd, rs, ((rm) << 16)) \
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#define aa64_emit_bic(rd, rs, rm) \
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aa64_emit_inst(logic, 0, rd, rs, ((rm) << 16) | (1 << 21)) \
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#define aa64_emit_add(rd, rs, rm) \
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aa64_emit_inst(addsub, 0, rd, rs, ((rm) << 16)) \
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#define aa64_emit_sub(rd, rs, rm) \
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aa64_emit_inst(addsub, 2, rd, rs, ((rm) << 16)) \
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#define aa64_emit_adc(rd, rs, rm) \
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aa64_emit_inst(misc, 0, rd, rs, ((rm) << 16)) \
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#define aa64_emit_sbc(rd, rs, rm) \
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aa64_emit_inst(misc, 2, rd, rs, ((rm) << 16)) \
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#define aa64_emit_adds(rd, rs, rm) \
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aa64_emit_inst(addsub, 1, rd, rs, ((rm) << 16)) \
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#define aa64_emit_subs(rd, rs, rm) \
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aa64_emit_inst(addsub, 3, rd, rs, ((rm) << 16)) \
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#define aa64_emit_adcs(rd, rs, rm) \
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aa64_emit_inst(misc, 1, rd, rs, ((rm) << 16)) \
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#define aa64_emit_sbcs(rd, rs, rm) \
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aa64_emit_inst(misc, 3, rd, rs, ((rm) << 16)) \
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#define aa64_emit_adr(rd, offset) \
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aa64_emit_inst(adr, (offset) & 3, rd, 0, ((offset) >> 2) & 0x7ffff) \
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#define aa64_emit_tbz(rd, bitn, offset) \
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aa64_emit_inst(tbz, 1, rd, 0, ((((u32)(offset)) & 0x3fff) << 5) | ((bitn) << 19))
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#define aa64_emit_tbnz(rd, bitn, offset) \
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aa64_emit_inst(tbnz, 1, rd, 0, ((((u32)(offset)) & 0x3fff) << 5) | ((bitn) << 19))
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#define aa64_emit_cbz(rd, offset) \
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aa64_emit_inst(b, 1, rd, 0, ((((u32)offset) & 0x7ffff)) << 5) \
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#define aa64_emit_cbnz(rd, offset) \
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aa64_emit_inst(b2, 1, rd, 0, ((((u32)offset) & 0x7ffff)) << 5) \
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/* Misc Operations: Cond-select, Cond-Compare, ADC/SBC, CLZ/O, REV ... */
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#define aa64_emit_csel(rd, rtrue, rfalse, cond) \
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aa64_emit_inst(misc, 0, rd, rtrue, (1<<23)|((rfalse) << 16)|((cond) << 12)) \
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#define aa64_emit_csinc(rd, rs, rm, cond) \
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aa64_emit_inst(misc, 0, rd, rs, 0x800400 | ((rm) << 16) | ((cond) << 12)) \
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#define aa64_emit_csinv(rd, rs, rm, cond) \
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aa64_emit_inst(misc, 2, rd, rs, 0x800000 | ((rm) << 16) | ((cond) << 12)) \
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#define aa64_emit_csneg(rd, rs, rm, cond) \
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aa64_emit_inst(misc, 2, rd, rs, 0x800400 | ((rm) << 16) | ((cond) << 12)) \
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#define aa64_emit_ubfm(rd, rs, imms, immr) \
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aa64_emit_inst(bfm, 2, rd, rs, ((imms) << 10) | ((immr) << 16)) \
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#define aa64_emit_ubfx(rd, rs, pos, size) \
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aa64_emit_ubfm(rd, rs, pos + size - 1, pos) \
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#define aa64_emit_cset(rd, cond) \
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aa64_emit_csinc(rd, 31, 31, ((cond) ^ 1)) \
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#define aa64_emit_csetm(rd, cond) \
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aa64_emit_csinv(rd, 31, 31, ((cond) ^ 1)) \
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#define aa64_emit_ccmpi(rn, immv, flags, cond) \
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aa64_emit_inst(misc, 3, rn, flags, 0x400800 | ((immv)<<16) | ((cond)<<12)) \
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#define aa64_emit_rorv(rd, rs, ra) \
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aa64_emit_inst(misc, 0, rd, rs, ((ra) << 16) | 0xC02C00) \
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#define aa64_emit_lslv(rd, rs, ra) \
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aa64_emit_inst(misc, 0, rd, rs, ((ra) << 16) | 0xC02000) \
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#define aa64_emit_lsrv(rd, rs, ra) \
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aa64_emit_inst(misc, 0, rd, rs, ((ra) << 16) | 0xC02400) \
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#define aa64_emit_asrv(rd, rs, ra) \
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aa64_emit_inst(misc, 0, rd, rs, ((ra) << 16) | 0xC02800) \
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#define aa64_emit_orr_shift64(rd, rs, rm, st, sa) \
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aa64_emit_inst(logic, 5, rd, rs, ((rm) << 16) | ((st)<<22) | ((sa)<<10)) \
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#define aa64_emit_merge_regs(rd, rhi, rlo) \
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aa64_emit_orr_shift64(rd, rlo, rhi, 0, 32) \
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#define aa64_emit_sdiv(rd, rs, rm) \
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aa64_emit_inst(misc, 0, rd, rs, ((rm) << 16) | 0xC00C00) \
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