[ARM] Rewrite HLE emulation for div, make it faster and simpler.
Moves the handlers to the cache, removes C usage.
This commit is contained in:
David Guillen Fandos
parent
b65df123f8
commit
f65c3939b5
3 changed files with 89 additions and 51 deletions
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@ -249,6 +249,9 @@ typedef enum {
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ARMOP_MUL = 0x0, /* Rd := Rm*Rs */
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ARMOP_MLA = 0x1, /* Rd := (Rm*Rs)+Rn */
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/* ARM7+ */
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ARMOP_MLS = 0x3, /* Rd := Rn-(Rm*Rs) */
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/* ARM3M+ */
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ARMOP_UMULL = 0x4,
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ARMOP_UMLAL = 0x5,
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@ -648,6 +651,11 @@ typedef struct {
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#define ARM_IASM_MLAS(rd, rm, rs, rn) \
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ARM_IASM_MLAS_COND(rd, rm, rs, rn, ARMCOND_AL)
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/* Rd := Rn - (Rm * Rs); 32x32+32->32 */
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#define ARM_MLS_COND(p, rd, rm, rs, rn, cond) \
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ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MLS, rd, rm, rs, rn, 0, cond))
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#define ARM_MLS(p, rd, rm, rs, rn) \
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ARM_MLS_COND(p, rd, rm, rs, rn, ARMCOND_AL)
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#define ARM_SMULL_COND(p, rn, rd, rm, rs, cond) \
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ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_SMULL, rd, rm, rs, rn, 0, cond))
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@ -1405,5 +1413,18 @@ typedef union {
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arminstr_t raw;
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} ARMInstr;
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/* ARMv7VE and others */
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#define ARM_SDIV_COND(p, rd, rm, rn, cond) \
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ARM_DEF_DPI_REG_REGSHIFT_COND(rm, 0, rn, 31, rd, 1, 0x38, cond)
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#define ARM_SDIV(p, rd, rm, rn) \
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ARM_SDIV_COND(p, rd, rm, rn, ARMCOND_AL)
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#define ARM_UDIV_COND(p, rd, rm, rn, cond) \
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ARM_DEF_DPI_REG_REGSHIFT_COND(rm, 0, rn, 31, rd, 1, 0x39, cond)
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#define ARM_UDIV(p, rd, rm, rn) \
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ARM_UDIV_COND(p, rd, rm, rn, ARMCOND_AL)
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#endif /* ARM_CG_H */
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100
arm/arm_emit.h
100
arm/arm_emit.h
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@ -1924,40 +1924,14 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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/* We're in ARM mode now */ \
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generate_branch(arm) \
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void execute_swi_hle_div_arm(void);
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void execute_swi_hle_div_thumb(void);
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void execute_swi_hle_divarm_arm(void);
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void execute_swi_hle_divarm_thumb(void);
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void execute_swi_hle_div_c(void)
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{
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/* real BIOS supposedly locks up, but game can recover on interrupt */
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if (reg[1] == 0)
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return;
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s32 result = (s32)reg[0] / (s32)reg[1];
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reg[1] = (s32)reg[0] % (s32)reg[1];
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reg[0] = result;
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reg[3] = (result ^ (result >> 31)) - (result >> 31);
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}
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void execute_swi_hle_divarm_c(void)
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{
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/* real BIOS supposedly locks up, but game can recover on interrupt */
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if (reg[0] == 0)
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return;
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s32 result = (s32)reg[1] / (s32)reg[0];
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reg[1] = (s32)reg[1] % (s32)reg[0];
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reg[0] = result;
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reg[3] = (result ^ (result >> 31)) - (result >> 31);
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}
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// Use software division
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void *div6, *divarm7;
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#define arm_hle_div(cpu_mode) \
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generate_function_call(execute_swi_hle_div_##cpu_mode);
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cycle_count += 11 + 32; \
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generate_function_call(div6);
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#define arm_hle_div_arm(cpu_mode) \
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generate_function_call(execute_swi_hle_divarm_##cpu_mode);
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cycle_count += 14 + 32; \
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generate_function_call(divarm7);
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#define generate_translation_gate(type) \
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generate_update_pc(pc); \
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@ -1968,9 +1942,71 @@ extern u32 ldst_handler_functions[9][17];
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extern u32 ldst_lookup_tables[9][17];
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void init_emitter(void) {
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int i;
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// Generate handler table
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memcpy(ldst_lookup_tables, ldst_handler_functions, sizeof(ldst_lookup_tables));
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rom_cache_watermark = 0;
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u8 *translation_ptr = (u8*)&rom_translation_cache[0];
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// Generate ARMv5+ division code, uses a mix of libgcc and some open bioses.
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// This is meant for ARMv5 or higher, uses CLZ
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// Invert operands for SWI 7 (divarm)
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divarm7 = translation_ptr;
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ARM_MOV_REG_REG(0, reg_a2, reg_x0);
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ARM_MOV_REG_REG(0, reg_x0, reg_x1);
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ARM_MOV_REG_REG(0, reg_x1, reg_a2);
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div6 = translation_ptr;
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// Save flags before using them
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generate_save_flags();
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// Stores result and remainder signs
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ARM_ANDS_REG_IMM(0, reg_a2, reg_x1, 0x80, arm_imm_lsl_to_rot(24));
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ARM_EOR_REG_IMMSHIFT(0, reg_a2, reg_a2, reg_x0, ARMSHIFT_ASR, 1);
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// Make numbers positive if they are negative
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ARM_RSB_REG_IMM_COND(0, reg_x1, reg_x1, 0, 0, ARMCOND_MI);
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ARM_TST_REG_REG(0, reg_x0, reg_x0);
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ARM_RSB_REG_IMM_COND(0, reg_x0, reg_x0, 0, 0, ARMCOND_MI);
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// Calculates the number of iterations to division, and jumps to unrolled code
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ARM_CLZ(0, reg_a0, reg_x0);
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ARM_CLZ(0, reg_a1, reg_x1);
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ARM_SUBS_REG_REG(0, reg_a0, reg_a1, reg_a0); // Align and check if a<b
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ARM_RSB_REG_IMM(0, reg_a0, reg_a0, 31, 0);
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ARM_MOV_REG_IMM_COND(0, reg_a0, 32, 0, ARMCOND_MI); // Cap to 32 (skip division)
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ARM_ADD_REG_IMMSHIFT(0, reg_a0, reg_a0, reg_a0, ARMSHIFT_LSL, 1);
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ARM_MOV_REG_IMM(0, reg_a1, 0, 0);
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ARM_ADD_REG_IMMSHIFT(0, ARMREG_PC, ARMREG_PC, reg_a0, ARMSHIFT_LSL, 2);
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ARM_NOP(0);
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for (i = 31; i >= 0; i--) {
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ARM_CMP_REG_IMMSHIFT(0, reg_x0, reg_x1, ARMSHIFT_LSL, i);
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ARM_ADC_REG_REG(0, reg_a1, reg_a1, reg_a1);
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ARM_SUB_REG_IMMSHIFT_COND(0, reg_x0, reg_x0, reg_x1, ARMSHIFT_LSL, i, ARMCOND_HS);
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}
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ARM_MOV_REG_REG(0, reg_x1, reg_x0);
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ARM_MOV_REG_REG(0, reg_x0, reg_a1);
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// Negate result if sign is negative
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ARM_SHLS_IMM(0, reg_a2, reg_a2, 1);
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ARM_RSB_REG_IMM_COND(0, reg_x0, reg_x0, 0, 0, ARMCOND_HS);
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ARM_RSB_REG_IMM_COND(0, reg_x1, reg_x1, 0, 0, ARMCOND_MI);
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// Register R3 stores the abs(r0/r1), store it in the right reg/mem-reg
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arm_generate_load_reg(reg_a2, REG_CPSR);
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ARM_TST_REG_IMM8(0, reg_a2, 0x20);
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arm_generate_store_reg(reg_a1, 3 /* r3 */);
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ARM_MOV_REG_REG_COND(0, reg_x3, reg_a1, ARMCOND_NE);
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// Return and continue regular emulation
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generate_restore_flags();
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ARM_BX(0, ARMREG_LR);
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// Now generate BIOS hooks
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rom_cache_watermark = (u32)(translation_ptr - rom_translation_cache);
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init_bios_hooks();
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}
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@ -397,25 +397,6 @@ execute_swi_builder(arm)
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execute_swi_builder(thumb)
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@ Wrapper for calling SWI functions in C (or can implement some in ASM if
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@ desired)
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#define execute_swi_function_builder(swi_function, mode) ;\
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;\
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defsymbl(execute_swi_hle_##swi_function##_##mode) ;\
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save_flags() ;\
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store_registers_##mode() ;\
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call_c_function(execute_swi_hle_##swi_function##_c) ;\
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load_registers_##mode() ;\
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restore_flags() ;\
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bx lr ;\
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execute_swi_function_builder(div, arm)
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execute_swi_function_builder(div, thumb)
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execute_swi_function_builder(divarm, arm)
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execute_swi_function_builder(divarm, thumb)
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@ Start program execution. Normally the mode should be Thumb and the
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@ PC should be 0x8000000, however if a save state is preloaded this
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@ will be different.
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