Implement dual mode (arm/thumb) for RAM positions
(This is similar to 908fb8 but for memory regions) Removes the weird offset encoding in favour of a metadata structure, similar to what there was before. However this structure overlaps with the cache ram itself and grows like a stack. This is to avoid wating memory since most games only use a few blocks. Simplify the "dual" block lookup routines too, since they are only an extrypoint to the other two real modes.
This commit is contained in:
David Guillen Fandos
parent
8036ad5b50
commit
f597836abc
150
cpu_threaded.c
150
cpu_threaded.c
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@ -2490,21 +2490,46 @@ void translate_icache_sync() {
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// 0x0000 : this is just data (never translated)
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// 0x00XX : not used (since first byte is zero)
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// 0x0101 : this is code that is not the start of a translated block
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// 0x0105 : first possible tag (we do not use 103 due to arm asm immediates)
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// 0xXXXX : this is the start of a translated block
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// 0xXXXX : this is the start of a translated block, starting from 0xFFFF downwards
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// LSB is always set (we decrement by two) to ensure both bytes != 0
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//
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// The tag value is a pointer to the ram cache where the translated block starts
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// The tag value must have both bytes set to non-zero, therefore the LSB is
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// always 1 and starts from 0x0101 value.
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// The 15 value is an index to 16 byte blocks in the RAM CACHE, therefore this
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// cache is limited to ~ 2^15 * 16byte ~= 512KB
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// The tag value is an index to a `ramtag_type` structure that sits at the end
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// of the RAM CACHE (grows like a stack). For simplicity we start tags at 0xFFFF
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// and grow like a stack.
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#define LAST_TAG_NUM 0x0101
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#define INITIAL_TOP_TAG 0xFFFF
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#define CODE_TAG_BLOCK16 0x0101
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#define CODE_TAG_BLOCK32 0x01010101
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#define INITIAL_TOP_TAG 0x0105
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#define TAG2ADDR(tag) (&ram_translation_cache[((((tag) - INITIAL_TOP_TAG) >> 1) << 4)])
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#define ADDR2TAG(addr) ((((((u8*)addr) - &ram_translation_cache[0]) >> 4) << 1) + INITIAL_TOP_TAG)
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#define VALIDTAG(tag) (tag >= INITIAL_TOP_TAG)
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#define VALID_TAG(tagn) (tagn > LAST_TAG_NUM)
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#define allocate_tag_arm(location) { \
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location[0] = ram_block_tag; \
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/* Could be another thumb inst */ \
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if (!location[1]) \
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location[1] = CODE_TAG_BLOCK16; \
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ram_block_tag -= 2; \
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}
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#define allocate_tag_thumb(location) { \
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location[0] = ram_block_tag; \
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ram_block_tag -= 2; \
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}
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typedef struct
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{
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u32 offset_arm; // Cache offset to the ARM-mode compiled block
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u32 offset_thumb; // Cache offset to the Thumb-mode compiled block
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} ramtag_type;
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static u32 ram_block_tag = INITIAL_TOP_TAG;
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inline static ramtag_type* get_ram_tag(u16 tagval) {
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ramtag_type *tbl = (ramtag_type*)&ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE];
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s16 tgidx = (s16)(tagval);
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return &tbl[tgidx >> 1]; /* Since LSB is always 1 and thus unused */
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}
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// This function will return a pointer to a translated block of code. If it
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// doesn't exist it will translate it, if it does it will pass it back.
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@ -2521,20 +2546,6 @@ void translate_icache_sync() {
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u32 thumb = 1; \
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pc &= ~0x01 \
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#define block_lookup_address_pc_dual() \
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u32 thumb = pc & 0x01; \
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\
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if(thumb) \
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{ \
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pc--; \
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reg[REG_CPSR] |= 0x20; \
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} \
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else \
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{ \
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pc = (pc + 2) & ~0x03; \
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reg[REG_CPSR] &= ~0x20; \
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} \
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#define ram_translation_region TRANSLATION_REGION_RAM
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#define rom_translation_region TRANSLATION_REGION_ROM
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@ -2546,51 +2557,33 @@ void translate_icache_sync() {
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translation_result = translate_block_thumb(pc, \
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mem_type##_translation_region, smc_enable) \
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#define block_lookup_translate_dual(mem_type, smc_enable) \
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if(thumb) \
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{ \
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translation_result = translate_block_thumb(pc, \
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mem_type##_translation_region, smc_enable); \
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#define block_lookup_translate_ram(inst_type) \
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{ \
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ramtag_type* trentry; \
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/* Allocate a tag if not a valid one, and initialize header */ \
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if (!VALID_TAG(*location)) { \
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allocate_tag_##inst_type(location); \
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trentry = get_ram_tag(*location); \
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trentry->offset_arm = 0; \
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trentry->offset_thumb = 0; \
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} else { \
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trentry = get_ram_tag(*location); \
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} \
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else \
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{ \
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translation_result = translate_block_arm(pc, \
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mem_type##_translation_region, smc_enable); \
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} \
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#define fill_tag_arm(tag) \
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location[0] = (tag); \
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location[1] = CODE_TAG_BLOCK16
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#define fill_tag_thumb(tag) \
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*location = (tag)
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#define fill_tag_dual(tag) \
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if(thumb) \
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fill_tag_thumb(tag); \
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else { \
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fill_tag_arm(tag); \
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} \
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#define block_lookup_translate_ram(instruction_type) \
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block_tag = *location; \
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if(!VALIDTAG(block_tag)) \
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\
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if (trentry->offset_##inst_type == 0) \
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{ \
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__label__ redo; \
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s32 translation_result; \
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\
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redo: \
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\
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/* Pad the start of the block to 16 bytes, see "memory tagging" above */ \
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while (((uintptr_t)(&ram_translation_ptr[block_prologue_size] \
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- ram_translation_cache)) % 16) \
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ram_translation_ptr++; \
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\
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translation_recursion_level++; \
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block_address = ram_translation_ptr + block_prologue_size; \
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fill_tag_##instruction_type(ADDR2TAG(block_address)); \
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trentry->offset_##inst_type = block_address - ram_translation_cache; \
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\
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translation_result = translate_block_##inst_type( \
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pc, ram_translation_region, 1); \
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\
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block_lookup_translate_##instruction_type(ram, 1); \
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translation_recursion_level--; \
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\
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/* If the translation failed then pass that failure on if we're in \
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@ -2608,8 +2601,9 @@ void translate_icache_sync() {
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} \
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else \
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{ \
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block_address = (u8*)TAG2ADDR(block_tag); \
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block_address = &ram_translation_cache[trentry->offset_##inst_type]; \
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} \
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}
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u32 translation_recursion_level = 0;
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u32 translation_flush_count = 0;
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@ -2665,7 +2659,7 @@ u8 function_cc *block_lookup_address_##type(u32 pc) \
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if(!blk_offset) \
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{ \
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__label__ redo; \
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s32 translation_result; \
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s32 result; \
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\
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redo: \
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\
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@ -2676,12 +2670,12 @@ u8 function_cc *block_lookup_address_##type(u32 pc) \
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*blk_offset_addr = (u32)(rom_translation_ptr - rom_translation_cache);\
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rom_translation_ptr += sizeof(hashhdr_type); \
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block_address = rom_translation_ptr + block_prologue_size; \
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block_lookup_translate_##type(rom, 0); \
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result = translate_block_##type(pc, rom_translation_region, 0); \
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translation_recursion_level--; \
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\
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/* If the translation failed then pass that failure on if we're in \
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a recursive level, or try again if we've hit the bottom. */ \
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if(translation_result == -1) \
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if(result == -1) \
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{ \
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if(translation_recursion_level) \
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return NULL; \
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@ -2717,7 +2711,20 @@ u8 function_cc *block_lookup_address_##type(u32 pc) \
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block_lookup_address_builder(arm);
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block_lookup_address_builder(thumb);
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block_lookup_address_builder(dual);
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u8 function_cc *block_lookup_address_dual(u32 pc)
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{
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u32 thumb = pc & 0x01;
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if(thumb) {
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pc &= ~1;
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reg[REG_CPSR] |= 0x20;
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return block_lookup_address_thumb(pc);
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} else {
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pc = (pc + 2) & ~0x03;
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reg[REG_CPSR] &= ~0x20;
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return block_lookup_address_arm(pc);
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}
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}
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// Potential exit point: If the rd field is pc for instructions is 0x0F,
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// the instruction is b/bl/bx, or the instruction is ldm with PC in the
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@ -3093,9 +3100,9 @@ s32 translate_block_arm(u32 pc, translation_region_type
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{
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case TRANSLATION_REGION_RAM:
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translation_ptr = ram_translation_ptr;
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translation_cache_limit =
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ram_translation_cache + RAM_TRANSLATION_CACHE_SIZE -
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TRANSLATION_CACHE_LIMIT_THRESHOLD;
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translation_cache_limit = &ram_translation_cache[
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RAM_TRANSLATION_CACHE_SIZE - TRANSLATION_CACHE_LIMIT_THRESHOLD
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- (0x10000 - ram_block_tag) / 2 * sizeof(ramtag_type)];
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break;
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case TRANSLATION_REGION_ROM:
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@ -3276,9 +3283,9 @@ s32 translate_block_thumb(u32 pc, translation_region_type
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{
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case TRANSLATION_REGION_RAM:
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translation_ptr = ram_translation_ptr;
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translation_cache_limit =
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ram_translation_cache + RAM_TRANSLATION_CACHE_SIZE -
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TRANSLATION_CACHE_LIMIT_THRESHOLD;
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translation_cache_limit = &ram_translation_cache[
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RAM_TRANSLATION_CACHE_SIZE - TRANSLATION_CACHE_LIMIT_THRESHOLD
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- (0x10000 - ram_block_tag) / 2 * sizeof(ramtag_type)];
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break;
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case TRANSLATION_REGION_ROM:
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@ -3463,6 +3470,7 @@ void flush_translation_cache_ram(void)
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iwram_code_max = 0U;
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ewram_code_min = ~0U;
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ewram_code_max = 0U;
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ram_block_tag = INITIAL_TOP_TAG;
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}
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void flush_translation_cache_rom(void)
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@ -11,15 +11,14 @@
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#if defined(SMALL_TRANSLATION_CACHE)
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 1024 * 2)
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#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 2)
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#else
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#define ROM_TRANSLATION_CACHE_SIZE (1024 * 1024 * 10)
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#define RAM_TRANSLATION_CACHE_SIZE (1024 * 512)
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 8)
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#endif
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/* Please note that RAM_TRANSLATION_CACHE_SIZE is limited to 512KB
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Check cpu_threaded.c for "memory tagging" for more info. */
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/* Should be an upperbound to the maximum number of bytes a single JIT'ed
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instruction can take. STM/LDM are tipically the biggest ones */
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#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 2)
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/* Hash table size for ROM trans cache lookups */
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#define ROM_BRANCH_HASH_BITS 16
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